From cc6877df9ec13b7f509921fe37a1f54914170aa2 Mon Sep 17 00:00:00 2001
From: Sebastien Bourdeauducq <sb@m-labs.hk>
Date: Mon, 27 Jul 2015 01:51:52 +0800
Subject: [PATCH] fhdl: allow use of ResetSignal() on resetless clock domains

---
 migen/fhdl/structure.py |  6 +++++-
 migen/fhdl/tools.py     | 10 +++++++++-
 2 files changed, 14 insertions(+), 2 deletions(-)

diff --git a/migen/fhdl/structure.py b/migen/fhdl/structure.py
index 45ab79452..b474e856e 100644
--- a/migen/fhdl/structure.py
+++ b/migen/fhdl/structure.py
@@ -327,10 +327,14 @@ class ResetSignal(Value):
     ----------
     cd : str
         Clock domain to obtain a reset signal for. Defaults to `"sys"`.
+    allow_resetless : bool
+        If the clock domain is resetless, return 0 instead of reporting an
+        error.
     """
-    def __init__(self, cd="sys"):
+    def __init__(self, cd="sys", allow_resetless=False):
         Value.__init__(self)
         self.cd = cd
+        self.allow_resetless = allow_resetless
 
 # statements
 
diff --git a/migen/fhdl/tools.py b/migen/fhdl/tools.py
index 685f4df37..f9f62f789 100644
--- a/migen/fhdl/tools.py
+++ b/migen/fhdl/tools.py
@@ -191,7 +191,15 @@ class _BasicLowerer(_Lowerer):
         return self.clock_domains[node.cd].clk
 
     def visit_ResetSignal(self, node):
-        return self.clock_domains[node.cd].rst
+        rst = self.clock_domains[node.cd].rst
+        if rst is None:
+            if node.allow_resetless:
+                return 0
+            else:
+                raise ValueError("Attempted to get reset signal of resetless"
+                                 " domain '{}'".format(node.cd))
+        else:
+            return rst
 
 
 class _ComplexSliceLowerer(_Lowerer):