From ccbfce920a37f8eb5f39122c0ae3f243d41251cb Mon Sep 17 00:00:00 2001 From: David A Roberts Date: Thu, 4 Apr 2024 17:43:27 +1000 Subject: [PATCH] soc/integration: Improve error handling for framebuffer without sdram --- litex/soc/integration/soc.py | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py index b570fd2b2..6d0b590d4 100644 --- a/litex/soc/integration/soc.py +++ b/litex/soc/integration/soc.py @@ -2367,10 +2367,14 @@ class LiteXSoC(SoC): size = 0x800000 # If the intended region isn't contained in the main_ram region, adjust it to fit. main_ram_region = self.bus.regions.get("main_ram", None) - if main_ram_region is not None and not ( + if main_ram_region is None: + self.logger.error("Video framebuffer requires SDRAM") + raise SoCError() + contained_in_main_ram = ( main_ram_region.origin < base and base + size < main_ram_region.origin + main_ram_region.size - ): + ) + if not contained_in_main_ram: size = min(size, main_ram_region.size // 2) base = main_ram_region.origin + main_ram_region.size - size self.bus.add_region(name, SoCRegion( @@ -2381,6 +2385,9 @@ class LiteXSoC(SoC): base = self.bus.regions[name].origin hres = int(timings.split("@")[0].split("x")[0]) vres = int(timings.split("@")[0].split("x")[1]) + if not hasattr(self, "sdram"): + self.logger.error("Video framebuffer requires SDRAM") + raise SoCError() vfb = VideoFrameBuffer(self.sdram.crossbar.get_port(), hres = hres, vres = vres,