diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py
index 4f6eee886..87aa67d67 100755
--- a/litex/soc/integration/soc.py
+++ b/litex/soc/integration/soc.py
@@ -480,6 +480,7 @@ class SoCBusHandler(LiteXModule):
             "axi"     : axi.AXICrossbar,
         }[self.standard]
 
+        self._interconnect = None
         if len(self.masters) and len(self.slaves):
             # If 1 bus_master, 1 bus_slave and no address translation, use InterconnectPointToPoint.
             if ((len(self.masters) == 1)  and