From cd3364a4332de09603e78c2d233f8ddc9ca22d94 Mon Sep 17 00:00:00 2001 From: Andrew Dennison Date: Mon, 4 Mar 2024 01:18:28 +0000 Subject: [PATCH] litex/gen/verilog: use format_constant --- litex/gen/fhdl/verilog.py | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/litex/gen/fhdl/verilog.py b/litex/gen/fhdl/verilog.py index d8b0dad61..bebcd8fd9 100644 --- a/litex/gen/fhdl/verilog.py +++ b/litex/gen/fhdl/verilog.py @@ -29,6 +29,7 @@ from migen.fhdl.specials import Instance, Memory from litex.gen import LiteXContext from litex.gen.fhdl.namer import build_signal_namespace from litex.gen.fhdl.hierarchy import LiteXHierarchyExplorer +from litex.gen.format import format_constant from litex.build.tools import get_litex_git_revision @@ -165,10 +166,10 @@ _ieee_1800_2017_verilog_reserved_keywords = { # Print Constant ----------------------------------------------------------------------------------- def _generate_constant(node): - return "{sign}{bits}'d{value}".format( + return "{sign}{bits}'{value}".format( sign = "" if node.value >= 0 else "-", bits = str(node.nbits), - value = abs(node.value), + value = format_constant(abs(node.value), verilog=True), ), node.signed # Print Signal -------------------------------------------------------------------------------------