From cd503bc9af28e92116b17f0ace49756ae5d4e984 Mon Sep 17 00:00:00 2001 From: Gwenhael Goavec-Merou Date: Tue, 19 Dec 2023 21:25:59 +0100 Subject: [PATCH] build/efinix/ifacewriter: Titanium PLL's feedback clock --- litex/build/efinix/ifacewriter.py | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/litex/build/efinix/ifacewriter.py b/litex/build/efinix/ifacewriter.py index be480cb26..325e49d55 100644 --- a/litex/build/efinix/ifacewriter.py +++ b/litex/build/efinix/ifacewriter.py @@ -281,7 +281,6 @@ design.create("{2}", "{3}", "./../gateware", overwrite=True) if block["version"] == "V3": cmd += 'design.gen_pll_ref_clock("{}", pll_res="{}", refclk_src="EXTERNAL", refclk_name="{}", ext_refclk_no="{}", ext_refclk_type="LVDS_RX")\n\n' \ .format(name, block["resource"], block["input_clock_pad"], block["clock_no"]) - cmd += 'design.set_property("{}","FEEDBACK_MODE","CORE","PLL")\n\n'.format(name) else: cmd += 'design.set_property("{}","EXT_CLK","EXT_CLK{}","PLL")\n'.format(name, block["clock_no"]) @@ -329,7 +328,14 @@ design.create("{2}", "{3}", "./../gateware", overwrite=True) else: cmd += 'design.set_property("{}","CLKOUT{}_PHASE_SETTING","{}","PLL")\n'.format(name, i, clock[2] // 45) - if block["feedback"] == -1: + # Titanium has always a feedback (local: CLK0, CORE: any output) + if block["version"] == "V3": + feedback_clk = block["feedback"] + cmd += 'design.set_property("{}", "FEEDBACK_MODE", "{}", "PLL")\n'.format(name, "LOCAL" if feedback_clk < 1 else "CORE") + cmd += 'design.set_property("{}", "FEEDBACK_CLK", "CLK{}", "PLL")\n'.format(name, 0 if feedback_clk < 1 else feedback_clk) + + # auto_calc_pll_clock is always working with Titanium and only working when feedback is unused for Trion + if block["feedback"] == -1 or block["version"] == "V3": cmd += "target_freq = {\n" for i, clock in enumerate(block["clk_out"]): cmd += ' "CLKOUT{}_FREQ": "{}",\n'.format(i, clock[1] / 1e6) @@ -358,7 +364,7 @@ design.create("{2}", "{3}", "./../gateware", overwrite=True) cmd += 'print("#### {} ####")\n'.format(name) cmd += 'clksrc_info = design.trace_ref_clock("{}", block_type="PLL")\n'.format(name) cmd += 'pprint.pprint(clksrc_info)\n' - cmd += 'clock_source_prop = ["REFCLK_SOURCE", "CORE_CLK_PIN", "EXT_CLK", "REFCLK_FREQ", "RESOURCE"]\n' + cmd += 'clock_source_prop = ["REFCLK_SOURCE", "CORE_CLK_PIN", "EXT_CLK", "REFCLK_FREQ", "RESOURCE", "FEEDBACK_MODE", "FEEDBACK_CLK"]\n' for i, clock in enumerate(block["clk_out"]): cmd += 'clock_source_prop += ["CLKOUT{}_FREQ", "CLKOUT{}_PHASE", "CLKOUT{}_EN"]\n'.format(i, i, i) cmd += 'prop_map = design.get_property("{}", clock_source_prop, block_type="PLL")\n'.format(name)