diff --git a/litex/soc/cores/cpu/lm32/core.py b/litex/soc/cores/cpu/lm32/core.py
index f41345bbc..522a0377f 100644
--- a/litex/soc/cores/cpu/lm32/core.py
+++ b/litex/soc/cores/cpu/lm32/core.py
@@ -40,6 +40,7 @@ class LM32(CPU):
         self.ibus      = i = wishbone.Interface()
         self.dbus      = d = wishbone.Interface()
         self.interrupt = Signal(32)
+        self.buses     = [i, d]
 
         # # #