From cd8218779e0eb05c73785cd6b8866dc3215c1710 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 6 Oct 2023 10:10:22 +0200 Subject: [PATCH] soc/cores/video/VideoFramebuffer: Add VTG/DMA synchronization when DMA is enabled to simplify use. --- CHANGES.md | 1 + litex/soc/cores/video.py | 23 ++++++++++++++++++++--- 2 files changed, 21 insertions(+), 3 deletions(-) diff --git a/CHANGES.md b/CHANGES.md index decf7088a..6b8247477 100644 --- a/CHANGES.md +++ b/CHANGES.md @@ -9,6 +9,7 @@ cpu/neorv32 : Added Debug support and update core complex. cpu/vexriscv_smp : Added hardware breakpoints support. build/colognechip : Added initial support. + soc/cores/video : Added VTG/DMA synchronization stage to VideoFramebuffer. [> Changed ---------- diff --git a/litex/soc/cores/video.py b/litex/soc/cores/video.py index 97227ee09..76fe6ee77 100644 --- a/litex/soc/cores/video.py +++ b/litex/soc/cores/video.py @@ -692,8 +692,25 @@ class VideoFrameBuffer(LiteXModule): ] video_pipe_source = self.cdc.source - # Video Generation. - self.comb += [ + # Video Synchronization/Generation. + fsm = FSM(reset_state="VTG-SYNC") + fsm = ClockDomainsRenamer(clock_domain)(fsm) + fsm = ResetInserter()(fsm) + self.submodules += fsm + self.specials += MultiReg(self.dma.fsm.reset, fsm.reset, clock_domain) + fsm.act("VTG-SYNC", + vtg_sink.ready.eq(1), + If(vtg_sink.valid & vtg_sink.last, + NextState("DMA-SYNC") + ) + ) + fsm.act("DMA-SYNC", + video_pipe_source.ready.eq(1), + If(video_pipe_source.valid & video_pipe_source.last, + NextState("RUN") + ) + ) + fsm.act("RUN", vtg_sink.ready.eq(1), If(vtg_sink.valid & vtg_sink.de, video_pipe_source.connect(source, keep={"valid", "ready"}), @@ -701,7 +718,7 @@ class VideoFrameBuffer(LiteXModule): ), vtg_sink.connect(source, keep={"de", "hsync", "vsync"}), - ] + ) if (depth == 32): self.comb += [ source.r.eq(video_pipe_source.data[ 0: 8]),