From cdd216f6923a99f75d37b2a5a2e147089227bb63 Mon Sep 17 00:00:00 2001 From: Rafal Kolucki Date: Mon, 11 Apr 2022 17:19:03 +0200 Subject: [PATCH] test/test_wishbone: Add basic test for SRAM with burst cycles support Tests incrementing address burst cycle with linear and wrapped increments. Only 4-beat wrap burst is tested in `test_sram_burst_wrap` test. --- test/test_wishbone.py | 41 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/test/test_wishbone.py b/test/test_wishbone.py index c79c943d5..dc8d04219 100644 --- a/test/test_wishbone.py +++ b/test/test_wishbone.py @@ -56,3 +56,44 @@ class TestWishbone(unittest.TestCase): dut = DUT() run_simulation(dut, generator(dut)) + + def test_sram_burst(self): + def generator(dut): + yield from dut.wb.write(0x0000, 0x01234567, cti=0b010) + yield from dut.wb.write(0x0001, 0x89abcdef, cti=0b010) + yield from dut.wb.write(0x0002, 0xdeadbeef, cti=0b010) + yield from dut.wb.write(0x0003, 0xc0ffee00, cti=0b111) + self.assertEqual((yield from dut.wb.read(0x0000, cti=0b010)), 0x01234567) + self.assertEqual((yield from dut.wb.read(0x0001, cti=0b010)), 0x89abcdef) + self.assertEqual((yield from dut.wb.read(0x0002, cti=0b010)), 0xdeadbeef) + self.assertEqual((yield from dut.wb.read(0x0003, cti=0b111)), 0xc0ffee00) + + class DUT(Module): + def __init__(self): + self.wb = wishbone.Interface(bursting=True) + wishbone_mem = wishbone.SRAM(32, bus=self.wb) + self.submodules += wishbone_mem + + dut = DUT() + run_simulation(dut, generator(dut)) + + def test_sram_burst_wrap(self): + def generator(dut): + bte = 0b01 + yield from dut.wb.write(0x0001, 0x01234567, cti=0b010, bte=bte) + yield from dut.wb.write(0x0002, 0x89abcdef, cti=0b010, bte=bte) + yield from dut.wb.write(0x0003, 0xdeadbeef, cti=0b010, bte=bte) + yield from dut.wb.write(0x0000, 0xc0ffee00, cti=0b111, bte=bte) + self.assertEqual((yield from dut.wb.read(0x0001, cti=0b010, bte=bte)), 0x01234567) + self.assertEqual((yield from dut.wb.read(0x0002, cti=0b010, bte=bte)), 0x89abcdef) + self.assertEqual((yield from dut.wb.read(0x0003, cti=0b010, bte=bte)), 0xdeadbeef) + self.assertEqual((yield from dut.wb.read(0x0000, cti=0b111, bte=bte)), 0xc0ffee00) + + class DUT(Module): + def __init__(self): + self.wb = wishbone.Interface(bursting=True) + wishbone_mem = wishbone.SRAM(32, bus=self.wb) + self.submodules += wishbone_mem + + dut = DUT() + run_simulation(dut, generator(dut)) \ No newline at end of file