From ce0551b44aea0b3a010b47a800e16f6f8a1caaff Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 27 Sep 2021 09:04:44 +0200 Subject: [PATCH] cpu/rocket/core: Remove ResetInserter on adapters. Previously, the SoCController was only reseting the CPU, which required adding these ResetInserters. Now that the SoCController resets both CPU and peripherals these ResetInserters are redundant and no longer useful. --- litex/soc/cores/cpu/rocket/core.py | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/litex/soc/cores/cpu/rocket/core.py b/litex/soc/cores/cpu/rocket/core.py index 59eafa515..308eeb845 100644 --- a/litex/soc/cores/cpu/rocket/core.py +++ b/litex/soc/cores/cpu/rocket/core.py @@ -294,12 +294,10 @@ class RocketRV64(CPU): self.cpu_params.update({'i_resetctrl_hartIsInReset_%s'%i : Open() for i in range(num_cores)}) # Adapt AXI interfaces to Wishbone. - mmio_a2w = ResetInserter()(axi.AXI2Wishbone(mmio_axi, mmio_wb, base_address=0)) - self.comb += mmio_a2w.reset.eq(ResetSignal() | self.reset) # Note: Must be reset with the CPU. + mmio_a2w = axi.AXI2Wishbone(mmio_axi, mmio_wb, base_address=0) self.submodules += mmio_a2w - l2fb_a2w = ResetInserter()(axi.Wishbone2AXI(l2fb_wb, l2fb_axi, base_address=0)) - self.comb += l2fb_a2w.reset.eq(ResetSignal() | self.reset) # Note: Must be reset with the CPU. + l2fb_a2w = axi.Wishbone2AXI(l2fb_wb, l2fb_axi, base_address=0) self.submodules += l2fb_a2w # Add Verilog sources.