diff --git a/misoclib/com/liteusb/common.py b/misoclib/com/liteusb/common.py
index b27e8318f..2f6f9772e 100644
--- a/misoclib/com/liteusb/common.py
+++ b/misoclib/com/liteusb/common.py
@@ -4,17 +4,15 @@ from migen.actorlib.fifo import *
 from migen.flow.actor import EndpointDescription
 
 user_layout = EndpointDescription(
-    [    ("dst", 8),
-         ("length", 4*8),
-         ("error", 1),
-        ("d", 8)
+    [("dst", 8),
+     ("length", 4*8),
+     ("error", 1),
+     ("d", 8)
     ],
     packetized=True
 )
 
-phy_layout = [
-    ("d", 8)
-]
+phy_layout = [("d", 8)]
 
 
 class LiteUSBPipe:
diff --git a/misoclib/com/liteusb/core/depacketizer.py b/misoclib/com/liteusb/core/depacketizer.py
index cbc919e86..9ed1a0353 100644
--- a/misoclib/com/liteusb/core/depacketizer.py
+++ b/misoclib/com/liteusb/core/depacketizer.py
@@ -43,11 +43,11 @@ class LiteUSBDepacketizer(Module):
                     preamble[i].eq(preamble[i-1])
             )
         fsm.act("WAIT_SOP",
-            If(    (preamble[3] == 0x5A) &
-                (preamble[2] == 0xA5) &
-                (preamble[1] == 0x5A) &
-                (preamble[0] == 0xA5) &
-                sink.stb,
+            If((preamble[3] == 0x5A) &
+               (preamble[2] == 0xA5) &
+               (preamble[1] == 0x5A) &
+               (preamble[0] == 0xA5) &
+               sink.stb,
             NextState("RECEIVE_HEADER")
             ),
             sink.ack.eq(1),