diff --git a/top.py b/top.py
index 910b90ed2..1a0c1b52b 100644
--- a/top.py
+++ b/top.py
@@ -44,7 +44,7 @@ sdram_timing = lasmicon.TimingSettings(
 	tRFC=ns(70),
 	
 	CL=3,
-	read_latency=4,
+	read_latency=5,
 	write_latency=0,
 
 	read_time=32,
diff --git a/verilog/s6ddrphy/s6ddrphy.v b/verilog/s6ddrphy/s6ddrphy.v
index dc4a49b6e..9fb5cdc76 100644
--- a/verilog/s6ddrphy/s6ddrphy.v
+++ b/verilog/s6ddrphy/s6ddrphy.v
@@ -7,7 +7,7 @@
  *
  * Assert dfi_rddata_en in the same cycle as the read
  * command. The data will come back on dfi_rddata
- * 4 cycles later, along with the assertion of
+ * 5 cycles later, along with the assertion of
  * dfi_rddata_valid.
  *
  * This PHY only supports CAS Latency 3.