diff --git a/litex/soc/cores/cpu/__init__.py b/litex/soc/cores/cpu/__init__.py
index 9ae5b0ae0..73ceed968 100644
--- a/litex/soc/cores/cpu/__init__.py
+++ b/litex/soc/cores/cpu/__init__.py
@@ -19,7 +19,7 @@ class CPU(Module):
     clang_flags          = None
     linker_output_format = None
     interrupts           = {}
-    mem_map              = {}
+    mem_map              = {"csr": 0x82000000}
     io_regions           = {}
     use_rom              = False
 
diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py
index 00ff92038..f6567fa64 100644
--- a/litex/soc/integration/soc.py
+++ b/litex/soc/integration/soc.py
@@ -894,9 +894,23 @@ class SoC(Module):
             self.cpu.add_cfu(cfu_filename=cfu)
 
         # Update SoC with CPU constraints.
+        # IOs regions.
         for n, (origin, size) in enumerate(self.cpu.io_regions.items()):
             self.bus.add_region("io{}".format(n), SoCIORegion(origin=origin, size=size, cached=False))
-        self.mem_map.update(self.cpu.mem_map) # FIXME
+        # Mapping.
+        if isinstance(self.cpu, cpu.CPUNone):
+            # With CPUNone, give priority to User's mapping.
+            self.mem_map = {**self.cpu.mem_map, **self.mem_map}
+        else:
+            # Override User's mapping with CPU constrainted mapping (and warn User).
+            for n, origin in self.cpu.mem_map.items():
+                if n in self.mem_map.keys():
+                    self.logger.info("CPU {} {} mapping from {} to {}.".format(
+                        colorer("overriding", color="cyan"),
+                        colorer(n),
+                        colorer(f"0x{self.mem_map[n]:x}"),
+                        colorer(f"0x{self.cpu.mem_map[n]:x}")))
+            self.mem_map.update(self.cpu.mem_map)
 
         # Add Bus Masters/CSR/IRQs.
         if not isinstance(self.cpu, (cpu.CPUNone, cpu.Zynq7000)):
diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py
index 13565f600..94c3b3ae9 100644
--- a/litex/soc/integration/soc_core.py
+++ b/litex/soc/integration/soc_core.py
@@ -56,7 +56,6 @@ class SoCCore(LiteXSoC):
         "rom":      0x00000000,
         "sram":     0x01000000,
         "main_ram": 0x40000000,
-        "csr":      0x82000000,
     }
 
     def __init__(self, platform, clk_freq,