From ce5864983d9432fa8a3ce57516a89ee4156be0e5 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 30 Jul 2021 15:00:10 +0200 Subject: [PATCH] soc/add_cpu: Add memory mapping overrides to build log and make an exception for the CPUNone case. A regular CPU can provides specific mapping constraints and we are overriding provided mapping with these constraints. The case of CPUNone is different and we can do the opposite: Give priority to User's mapping. For the regular CPU case, the override was done silently, it is now logged during the build. --- litex/soc/cores/cpu/__init__.py | 2 +- litex/soc/integration/soc.py | 16 +++++++++++++++- litex/soc/integration/soc_core.py | 1 - 3 files changed, 16 insertions(+), 3 deletions(-) diff --git a/litex/soc/cores/cpu/__init__.py b/litex/soc/cores/cpu/__init__.py index 9ae5b0ae0..73ceed968 100644 --- a/litex/soc/cores/cpu/__init__.py +++ b/litex/soc/cores/cpu/__init__.py @@ -19,7 +19,7 @@ class CPU(Module): clang_flags = None linker_output_format = None interrupts = {} - mem_map = {} + mem_map = {"csr": 0x82000000} io_regions = {} use_rom = False diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py index 00ff92038..f6567fa64 100644 --- a/litex/soc/integration/soc.py +++ b/litex/soc/integration/soc.py @@ -894,9 +894,23 @@ class SoC(Module): self.cpu.add_cfu(cfu_filename=cfu) # Update SoC with CPU constraints. + # IOs regions. for n, (origin, size) in enumerate(self.cpu.io_regions.items()): self.bus.add_region("io{}".format(n), SoCIORegion(origin=origin, size=size, cached=False)) - self.mem_map.update(self.cpu.mem_map) # FIXME + # Mapping. + if isinstance(self.cpu, cpu.CPUNone): + # With CPUNone, give priority to User's mapping. + self.mem_map = {**self.cpu.mem_map, **self.mem_map} + else: + # Override User's mapping with CPU constrainted mapping (and warn User). + for n, origin in self.cpu.mem_map.items(): + if n in self.mem_map.keys(): + self.logger.info("CPU {} {} mapping from {} to {}.".format( + colorer("overriding", color="cyan"), + colorer(n), + colorer(f"0x{self.mem_map[n]:x}"), + colorer(f"0x{self.cpu.mem_map[n]:x}"))) + self.mem_map.update(self.cpu.mem_map) # Add Bus Masters/CSR/IRQs. if not isinstance(self.cpu, (cpu.CPUNone, cpu.Zynq7000)): diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py index 13565f600..94c3b3ae9 100644 --- a/litex/soc/integration/soc_core.py +++ b/litex/soc/integration/soc_core.py @@ -56,7 +56,6 @@ class SoCCore(LiteXSoC): "rom": 0x00000000, "sram": 0x01000000, "main_ram": 0x40000000, - "csr": 0x82000000, } def __init__(self, platform, clk_freq,