From ce5c58592b95d9115979de8e6a2069dc705ffd31 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Sun, 4 Aug 2019 12:22:35 +0200 Subject: [PATCH] soc/cores/uart: add FT245 FIFO mode support (sync & async) --- litex/soc/cores/uart.py | 14 ++++++++++++++ litex/soc/integration/soc_core.py | 2 +- 2 files changed, 15 insertions(+), 1 deletion(-) diff --git a/litex/soc/cores/uart.py b/litex/soc/cores/uart.py index 74263cec1..9a2d18676 100644 --- a/litex/soc/cores/uart.py +++ b/litex/soc/cores/uart.py @@ -13,6 +13,7 @@ from litex.soc.interconnect.csr_eventmanager import * from litex.soc.interconnect import stream from litex.soc.interconnect.wishbonebridge import WishboneStreamingBridge +# RS232 PHY ---------------------------------------------------------------------------------------- class RS232PHYInterface: def __init__(self): @@ -157,6 +158,7 @@ class RS232PHYModel(Module): pads.sink_ready.eq(self.source.ready) ] +# UART --------------------------------------------------------------------------------------------- def _get_uart_fifo(depth, sink_cd="sys", source_cd="sys"): if sink_cd != source_cd: @@ -165,6 +167,18 @@ def _get_uart_fifo(depth, sink_cd="sys", source_cd="sys"): else: return stream.SyncFIFO([("data", 8)], depth, buffered=True) +def UARTPHY(pads, clk_freq, baudrate): + # FT245 async FIFO mode (baudrate ignored) + if hasattr(pads, "rd_n") and hasattr(pads, "wr_n"): + from litex.soc.cores.usb_fifo import FT245PHYAsynchronous + return FT245PHYAsynchronous(pads, clk_freq) + # FT245 sync FIFO mode (baudrate ignored) + if hasattr(pads, "rd_n") and hasattr(pads, "wr_n") and hasattr(pads, "oe_n"): + from litex.soc.cores.usb_fifo import FT245PHYSynchronous + return FT245PHYSynchronous(pads, clk_freq) + # RS232 + else: + return RS232PHY(pads, clk_freq, baudrate) class UART(Module, AutoCSR): def __init__(self, phy, diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py index 744225db5..c70a9c90a 100644 --- a/litex/soc/integration/soc_core.py +++ b/litex/soc/integration/soc_core.py @@ -315,7 +315,7 @@ class SoCCore(Module): if uart_stub: self.submodules.uart = uart.UARTStub() else: - self.submodules.uart_phy = uart.RS232PHY(platform.request(uart_name), clk_freq, uart_baudrate) + self.submodules.uart_phy = uart.UARTPHY(platform.request(uart_name), clk_freq, uart_baudrate) self.submodules.uart = ResetInserter()(uart.UART(self.uart_phy)) self.add_csr("uart_phy", allow_user_defined=True) self.add_csr("uart", allow_user_defined=True)