From ce90181046cd12f567fcd3466c507606a3a87141 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Tue, 6 Sep 2022 13:13:45 +0200 Subject: [PATCH] cpu/VexRiscv_SMP add --wishbone-force-32b option --- litex/soc/cores/cpu/vexriscv_smp/core.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex/soc/cores/cpu/vexriscv_smp/core.py b/litex/soc/cores/cpu/vexriscv_smp/core.py index 1f9a8cbae..e6061c254 100755 --- a/litex/soc/cores/cpu/vexriscv_smp/core.py +++ b/litex/soc/cores/cpu/vexriscv_smp/core.py @@ -260,7 +260,7 @@ class VexRiscvSMP(CPU): gen_args.append(f"--aes-instruction={VexRiscvSMP.aes_instruction}") gen_args.append(f"--out-of-order-decoder={VexRiscvSMP.out_of_order_decoder}") gen_args.append(f"--wishbone-memory={VexRiscvSMP.wishbone_memory}") - gen_args.append(f"--wishbone-force-32b={VexRiscvSMP.wishbone_force_32b}") + if(VexRiscvSMP.wishbone_force_32b): gen_args.append(f"--wishbone-force-32b={VexRiscvSMP.wishbone_force_32b}") gen_args.append(f"--fpu={VexRiscvSMP.with_fpu}") gen_args.append(f"--cpu-per-fpu={VexRiscvSMP.cpu_per_fpu}") gen_args.append(f"--rvc={VexRiscvSMP.with_rvc}")