From cf084fd079b83f16b4d75011cdf84e9bf897bdf4 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Tue, 30 Sep 2014 09:29:15 +0200
Subject: [PATCH] test to visualize OOB with Miscope

---
 Makefile          |  2 +-
 targets/test.py   | 52 ++++++++++++++++++++++++++++++++++++++++++-----
 test/test_mila.py | 20 ++++++++++++++++++
 3 files changed, 68 insertions(+), 6 deletions(-)
 create mode 100644 test/test_mila.py

diff --git a/Makefile b/Makefile
index 3afe39351..51f03d588 100644
--- a/Makefile
+++ b/Makefile
@@ -7,7 +7,7 @@ PLATFORM = kc705_impact
 CMD = $(PYTHON) make.py -X $(CURDIR) -Op toolchain $(TOOLCHAIN) -p $(PLATFORM) -t test
 
 csv:
-	cd $(MSCDIR) && $(CMD) --csr_csv $(CURDIR)/test/csr.csv build-csr-csv
+	cd $(MSCDIR) && $(CMD) --csr_csv $(CURDIR)/test/csr.csv build-csr-csv -Ot gen_mila_csv True
 	cd $(CURDIR)
 
 bit:
diff --git a/targets/test.py b/targets/test.py
index 2af3bde30..b08987442 100644
--- a/targets/test.py
+++ b/targets/test.py
@@ -88,21 +88,63 @@ class UART2WB(Module):
 
 class TestDesign(UART2WB):
 	default_platform = "kc705"
+	csr_map = {
+		"mila":				10
+	}
+	csr_map.update(UART2WB.csr_map)
 
-	def __init__(self, platform):
+	def __init__(self, platform, **kwargs):
 		clk_freq = 166666*1000
 		UART2WB.__init__(self, platform, clk_freq)
 		self.submodules.crg = _CRG(platform)
 
-		self.submodules.sataphy_host = K7SATAPHY(platform.request("sata_host"), clk_freq, host=True)
+		self.submodules.sataphy_host = K7SATAPHY(platform.request("sata_host"), clk_freq, 
+			host=True, default_speed="SATA1")
 		self.comb += [
 			self.sataphy_host.sink.stb.eq(1),
 			self.sataphy_host.sink.d.eq(0x12345678)
 		]
-		self.submodules.sataphy_device = K7SATAPHY(platform.request("sata_device"), clk_freq, host=False)
+
+		import os
+		from miscope import trigger, miio, mila
+		from mibuild.tools import write_to_file
+		from migen.fhdl import verilog
+
+		term = trigger.Term(width=64)
+		self.submodules.mila = mila.MiLa(width=64, depth=2048, ports=[term], with_rle=True)
+
+		gtx = self.sataphy_host.gtx
+		ctrl = self.sataphy_host.ctrl
+
+		mila_dat = (
+			gtx.rxresetdone,
+			gtx.txresetdone,
+
+			gtx.rxuserrdy,
+			gtx.txuserrdy,
+
+			gtx.rxcominitdet,
+			gtx.rxcomwakedet,
+
+			gtx.txcomfinish,
+			gtx.txcominit,
+			gtx.txcomwake,
+
+		)
+
 		self.comb += [
-			self.sataphy_device.sink.stb.eq(1),
-			self.sataphy_device.sink.d.eq(0x12345678)
+			self.mila.sink.stb.eq(1),
+			self.mila.sink.dat.eq(Cat(*mila_dat))
 		]
 
+		try:
+			gen_mila_csv = kwargs.pop('gen_mila_csv')
+		except:
+			gen_mila_csv = False
+
+		if gen_mila_csv: 
+			r, ns = verilog.convert(self, return_ns=True)
+			mila_csv = self.mila.get_csv(mila_dat, ns)
+			write_to_file(os.path.join(platform.soc_ext_path, "test", "mila.csv"), mila_csv)
+
 default_subtarget = TestDesign
diff --git a/test/test_mila.py b/test/test_mila.py
new file mode 100644
index 000000000..79834a63a
--- /dev/null
+++ b/test/test_mila.py
@@ -0,0 +1,20 @@
+from config import *
+from miscope.host.drivers import MiLaDriver
+
+mila = MiLaDriver(wb.regs, "mila", use_rle=True)
+wb.open()
+###
+trigger0 = mila.sataphy_host_gtx_txcominit0_o
+mask0 = mila.sataphy_host_gtx_txcominit0_m
+
+mila.prog_term(port=0, trigger=trigger0, mask=mask0)
+mila.prog_sum("term")
+
+# Trigger / wait / receive
+mila.trigger(offset=8, length=64)
+mila.wait_done()
+mila.read()
+mila.export("dump.vcd")
+mila.export("dump.csv")
+###
+wb.close()