From cf2e073b14199f2b7dd839150593c6834edbcb84 Mon Sep 17 00:00:00 2001 From: Navaneeth Bhardwaj Date: Wed, 20 Oct 2021 07:28:13 +0530 Subject: [PATCH] Add changes to use Ibex from pythondata-cpu-ibex --- litex/soc/cores/cpu/ibex/core.py | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/litex/soc/cores/cpu/ibex/core.py b/litex/soc/cores/cpu/ibex/core.py index 44bda122c..046837ec3 100644 --- a/litex/soc/cores/cpu/ibex/core.py +++ b/litex/soc/cores/cpu/ibex/core.py @@ -189,8 +189,7 @@ class Ibex(CPU): @staticmethod def add_sources(platform): - opentitandir = get_data_mod("misc", "opentitan").data_location - ibexdir = os.path.join(os.path.join(opentitandir, "hw", "vendor", "lowrisc_ibex")) + ibexdir = get_data_mod("cpu", "ibex").data_location platform.add_sources(os.path.join(ibexdir, "rtl"), "ibex_pkg.sv", "ibex_alu.sv", @@ -222,12 +221,17 @@ class Ibex(CPU): platform.add_source("ibex_top.sv") platform.add_source(os.path.join(ibexdir, "syn", "rtl", "prim_clock_gating.v")) - platform.add_sources(os.path.join(opentitandir, "hw", "ip", "prim", "rtl"), + platform.add_sources(os.path.join(ibexdir, "vendor", "lowrisc_ip", "ip", "prim", "rtl"), "prim_alert_pkg.sv", "prim_assert.sv" ) - platform.add_verilog_include_path(os.path.join(opentitandir, "hw", "ip", "prim", "rtl")) - platform.add_verilog_include_path(os.path.join(opentitandir, "hw", "dv", "sv", "dv_utils")) + platform.add_verilog_include_path(os.path.join(ibexdir, "rtl")) + platform.add_verilog_include_path(os.path.join(ibexdir, + "vendor", "lowrisc_ip", "dv", "sv", "dv_utils") + ) + platform.add_verilog_include_path(os.path.join(ibexdir, + "vendor", "lowrisc_ip", "ip", "prim", "rtl") + ) def set_reset_address(self, reset_address): assert not hasattr(self, "reset_address")