diff --git a/make.py b/make.py index 8de6e09e2..99a12bb6f 100755 --- a/make.py +++ b/make.py @@ -7,7 +7,7 @@ from migen.util.misc import autotype from migen.fhdl import simplify from misoclib.gensoc import cpuif -from misoclib.sdramphy import initsequence +from misoclib.sdram.phy import initsequence from misoc_import import misoc_import diff --git a/misoclib/gensoc/__init__.py b/misoclib/gensoc/__init__.py index 661b1d109..d605a1a6d 100644 --- a/misoclib/gensoc/__init__.py +++ b/misoclib/gensoc/__init__.py @@ -8,8 +8,10 @@ from migen.bank import csrgen from migen.bus import wishbone, csr, lasmibus, dfi from migen.bus import wishbone2lasmi, wishbone2csr -from misoclib import lm32, mor1kx, uart, dfii, lasmicon, identifier, timer, memtest -from misoclib.lasmicon.minicon import Minicon +from misoclib import lm32, mor1kx, uart, identifier, timer, memtest +from misoclib.sdram import lasmicon +from misoclib.sdram import dfii +from misoclib.sdram.minicon import Minicon class GenSoC(Module): csr_base = 0xe0000000 diff --git a/misoclib/sdram/__init__.py b/misoclib/sdram/__init__.py new file mode 100644 index 000000000..f861d63cc --- /dev/null +++ b/misoclib/sdram/__init__.py @@ -0,0 +1,12 @@ +from collections import namedtuple + +PhySettingsT = namedtuple("PhySettings", "memtype dfi_d nphases rdphase wrphase rdcmdphase wrcmdphase cl cwl read_latency write_latency") +def PhySettings(memtype, dfi_d, nphases, rdphase, wrphase, rdcmdphase, wrcmdphase, cl, read_latency, write_latency, cwl=0): + return PhySettingsT(memtype, dfi_d, nphases, rdphase, wrphase, rdcmdphase, wrcmdphase, cl, cwl, read_latency, write_latency) + +GeomSettingsT = namedtuple("_GeomSettings", "bank_a row_a col_a mux_a") +def GeomSettings(bank_a, row_a, col_a): + return GeomSettingsT(bank_a, row_a, col_a, max(row_a, col_a)) + +TimingSettings = namedtuple("TimingSettings", "tRP tRCD tWR tWTR tREFI tRFC" \ + " req_queue_size read_time write_time") diff --git a/misoclib/dfii/__init__.py b/misoclib/sdram/dfii/__init__.py similarity index 100% rename from misoclib/dfii/__init__.py rename to misoclib/sdram/dfii/__init__.py diff --git a/misoclib/lasmicon/__init__.py b/misoclib/sdram/lasmicon/__init__.py similarity index 63% rename from misoclib/lasmicon/__init__.py rename to misoclib/sdram/lasmicon/__init__.py index 7dbf313fe..1136bcfe4 100644 --- a/misoclib/lasmicon/__init__.py +++ b/misoclib/sdram/lasmicon/__init__.py @@ -1,22 +1,9 @@ -from collections import namedtuple - from migen.fhdl.std import * from migen.bus import dfi, lasmibus -from misoclib.lasmicon.refresher import * -from misoclib.lasmicon.bankmachine import * -from misoclib.lasmicon.multiplexer import * - -PhySettingsT = namedtuple("PhySettings", "memtype dfi_d nphases rdphase wrphase rdcmdphase wrcmdphase cl cwl read_latency write_latency") -def PhySettings(memtype, dfi_d, nphases, rdphase, wrphase, rdcmdphase, wrcmdphase, cl, read_latency, write_latency, cwl=0): - return PhySettingsT(memtype, dfi_d, nphases, rdphase, wrphase, rdcmdphase, wrcmdphase, cl, cwl, read_latency, write_latency) - -GeomSettingsT = namedtuple("_GeomSettings", "bank_a row_a col_a mux_a") -def GeomSettings(bank_a, row_a, col_a): - return GeomSettingsT(bank_a, row_a, col_a, max(row_a, col_a)) - -TimingSettings = namedtuple("TimingSettings", "tRP tRCD tWR tWTR tREFI tRFC" \ - " req_queue_size read_time write_time") +from misoclib.sdram.lasmicon.refresher import * +from misoclib.sdram.lasmicon.bankmachine import * +from misoclib.sdram.lasmicon.multiplexer import * class LASMIcon(Module): def __init__(self, phy_settings, geom_settings, timing_settings): diff --git a/misoclib/lasmicon/bankmachine.py b/misoclib/sdram/lasmicon/bankmachine.py similarity index 98% rename from misoclib/lasmicon/bankmachine.py rename to misoclib/sdram/lasmicon/bankmachine.py index 9b08d28fd..53c43f0ac 100644 --- a/misoclib/lasmicon/bankmachine.py +++ b/misoclib/sdram/lasmicon/bankmachine.py @@ -4,7 +4,7 @@ from migen.genlib.fsm import FSM, NextState from migen.genlib.misc import optree from migen.genlib.fifo import SyncFIFO -from misoclib.lasmicon.multiplexer import * +from misoclib.sdram.lasmicon.multiplexer import * class _AddressSlicer: def __init__(self, col_a, address_align): diff --git a/misoclib/lasmicon/multiplexer.py b/misoclib/sdram/lasmicon/multiplexer.py similarity index 99% rename from misoclib/lasmicon/multiplexer.py rename to misoclib/sdram/lasmicon/multiplexer.py index f72bf86cc..cee6f1fd5 100644 --- a/misoclib/lasmicon/multiplexer.py +++ b/misoclib/sdram/lasmicon/multiplexer.py @@ -4,7 +4,7 @@ from migen.genlib.misc import optree from migen.genlib.fsm import FSM, NextState from migen.bank.description import AutoCSR -from misoclib.lasmicon.perf import Bandwidth +from misoclib.sdram.lasmicon.perf import Bandwidth class CommandRequest: def __init__(self, a, ba): diff --git a/misoclib/lasmicon/perf.py b/misoclib/sdram/lasmicon/perf.py similarity index 100% rename from misoclib/lasmicon/perf.py rename to misoclib/sdram/lasmicon/perf.py diff --git a/misoclib/lasmicon/refresher.py b/misoclib/sdram/lasmicon/refresher.py similarity index 96% rename from misoclib/lasmicon/refresher.py rename to misoclib/sdram/lasmicon/refresher.py index 76482bd4b..cb59fb866 100644 --- a/misoclib/lasmicon/refresher.py +++ b/misoclib/sdram/lasmicon/refresher.py @@ -2,7 +2,7 @@ from migen.fhdl.std import * from migen.genlib.misc import timeline from migen.genlib.fsm import FSM -from misoclib.lasmicon.multiplexer import * +from misoclib.sdram.lasmicon.multiplexer import * class Refresher(Module): def __init__(self, a, ba, tRP, tREFI, tRFC): diff --git a/misoclib/lasmicon/test/bankmachine.py b/misoclib/sdram/lasmicon/test/bankmachine.py similarity index 95% rename from misoclib/lasmicon/test/bankmachine.py rename to misoclib/sdram/lasmicon/test/bankmachine.py index d446fb0f8..a6719cf51 100644 --- a/misoclib/lasmicon/test/bankmachine.py +++ b/misoclib/sdram/lasmicon/test/bankmachine.py @@ -2,7 +2,7 @@ from migen.fhdl.std import * from migen.bus.lasmibus import * from migen.sim.generic import run_simulation -from misoclib.lasmicon.bankmachine import * +from misoclib.sdram.lasmicon.bankmachine import * from common import sdram_phy, sdram_geom, sdram_timing, CommandLogger diff --git a/misoclib/lasmicon/test/common.py b/misoclib/sdram/lasmicon/test/common.py similarity index 93% rename from misoclib/lasmicon/test/common.py rename to misoclib/sdram/lasmicon/test/common.py index c463297b9..3d60d704f 100644 --- a/misoclib/lasmicon/test/common.py +++ b/misoclib/sdram/lasmicon/test/common.py @@ -3,7 +3,7 @@ from math import ceil from migen.fhdl.std import * -from misoclib import lasmicon +from misoclib import sdram MHz = 1000000 clk_freq = (83 + Fraction(1, 3))*MHz @@ -14,7 +14,7 @@ def ns(t, margin=True): t += clk_period_ns/2 return ceil(t/clk_period_ns) -sdram_phy = lasmicon.PhySettings( +sdram_phy = sdram.PhySettings( memtype="DDR", dfi_d=64, nphases=2, @@ -27,12 +27,12 @@ sdram_phy = lasmicon.PhySettings( write_latency=0 ) -sdram_geom = lasmicon.GeomSettings( +sdram_geom = sdram.GeomSettings( bank_a=2, row_a=13, col_a=10 ) -sdram_timing = lasmicon.TimingSettings( +sdram_timing = sdram.TimingSettings( tRP=ns(15), tRCD=ns(15), tWR=ns(15), diff --git a/misoclib/lasmicon/test/lasmicon.py b/misoclib/sdram/lasmicon/test/lasmicon.py similarity index 96% rename from misoclib/lasmicon/test/lasmicon.py rename to misoclib/sdram/lasmicon/test/lasmicon.py index 05466d445..e4cd04585 100644 --- a/misoclib/lasmicon/test/lasmicon.py +++ b/misoclib/sdram/lasmicon/test/lasmicon.py @@ -2,7 +2,7 @@ from migen.fhdl.std import * from migen.bus.lasmibus import * from migen.sim.generic import run_simulation -from misoclib.lasmicon import * +from misoclib.sdram.lasmicon import * from common import sdram_phy, sdram_geom, sdram_timing, DFILogger diff --git a/misoclib/lasmicon/test/lasmicon_df.py b/misoclib/sdram/lasmicon/test/lasmicon_df.py similarity index 97% rename from misoclib/lasmicon/test/lasmicon_df.py rename to misoclib/sdram/lasmicon/test/lasmicon_df.py index b5380df5b..d2a4add11 100644 --- a/misoclib/lasmicon/test/lasmicon_df.py +++ b/misoclib/sdram/lasmicon/test/lasmicon_df.py @@ -3,7 +3,7 @@ from migen.bus import lasmibus from migen.actorlib import dma_lasmi from migen.sim.generic import run_simulation -from misoclib.lasmicon import * +from misoclib.sdram.lasmicon import * from common import sdram_phy, sdram_geom, sdram_timing, DFILogger diff --git a/misoclib/lasmicon/test/lasmicon_wb.py b/misoclib/sdram/lasmicon/test/lasmicon_wb.py similarity index 96% rename from misoclib/lasmicon/test/lasmicon_wb.py rename to misoclib/sdram/lasmicon/test/lasmicon_wb.py index 1a385ed9b..35d18d9b1 100644 --- a/misoclib/lasmicon/test/lasmicon_wb.py +++ b/misoclib/sdram/lasmicon/test/lasmicon_wb.py @@ -3,7 +3,7 @@ from migen.bus import wishbone, wishbone2lasmi, lasmibus from migen.bus.transactions import * from migen.sim.generic import run_simulation -from misoclib.lasmicon import * +from misoclib.sdram.lasmicon import * from common import sdram_phy, sdram_geom, sdram_timing, DFILogger diff --git a/misoclib/lasmicon/test/refresher.py b/misoclib/sdram/lasmicon/test/refresher.py similarity index 95% rename from misoclib/lasmicon/test/refresher.py rename to misoclib/sdram/lasmicon/test/refresher.py index 040b42db6..6437a781e 100644 --- a/misoclib/lasmicon/test/refresher.py +++ b/misoclib/sdram/lasmicon/test/refresher.py @@ -3,7 +3,7 @@ from random import Random from migen.fhdl.std import * from migen.sim.generic import run_simulation -from misoclib.lasmicon.refresher import * +from misoclib.sdram.lasmicon.refresher import * from common import CommandLogger diff --git a/misoclib/lasmicon/minicon.py b/misoclib/sdram/minicon/__init__.py similarity index 100% rename from misoclib/lasmicon/minicon.py rename to misoclib/sdram/minicon/__init__.py diff --git a/misoclib/lasmicon/minicontb.py b/misoclib/sdram/minicon/tb/minicontb.py similarity index 96% rename from misoclib/lasmicon/minicontb.py rename to misoclib/sdram/minicon/tb/minicontb.py index 8fb982b43..325da01cc 100755 --- a/misoclib/lasmicon/minicontb.py +++ b/misoclib/sdram/minicon/tb/minicontb.py @@ -4,9 +4,9 @@ from migen.bus import wishbone from migen.sim.generic import Simulator from migen.sim import icarus from mibuild.platforms import papilio_pro as board -from misoclib import lasmicon -from misoclib.lasmicon.minicon import Minicon -from misoclib.sdramphy import gensdrphy +from misoclib import sdram +from misoclib.sdram.minicon import Minicon +from misoclib.sdram.phy import gensdrphy from itertools import chain from os.path import isfile import sys @@ -153,13 +153,13 @@ if __name__ == "__main__": plat = board.Platform() - sdram_geom = lasmicon.GeomSettings( + sdram_geom = sdram.GeomSettings( bank_a=2, row_a=12, col_a=8 ) - sdram_timing = lasmicon.TimingSettings( + sdram_timing = sdram.TimingSettings( tRP=ns(15), tRCD=ns(15), tWR=ns(14), diff --git a/misoclib/sdramphy/gensdrphy.py b/misoclib/sdram/phy/gensdrphy.py similarity index 96% rename from misoclib/sdramphy/gensdrphy.py rename to misoclib/sdram/phy/gensdrphy.py index a065a9399..9abd1d009 100644 --- a/misoclib/sdramphy/gensdrphy.py +++ b/misoclib/sdram/phy/gensdrphy.py @@ -26,7 +26,7 @@ from migen.bus.dfi import * from migen.genlib.record import * from migen.fhdl.specials import * -from misoclib import lasmicon +from misoclib import sdram class GENSDRPHY(Module): def __init__(self, pads): @@ -34,7 +34,7 @@ class GENSDRPHY(Module): ba = flen(pads.ba) d = flen(pads.dq) - self.phy_settings = lasmicon.PhySettings( + self.phy_settings = sdram.PhySettings( memtype="SDR", dfi_d=d, nphases=1, diff --git a/misoclib/sdramphy/initsequence.py b/misoclib/sdram/phy/initsequence.py similarity index 100% rename from misoclib/sdramphy/initsequence.py rename to misoclib/sdram/phy/initsequence.py diff --git a/misoclib/sdramphy/k7ddrphy.py b/misoclib/sdram/phy/k7ddrphy.py similarity index 99% rename from misoclib/sdramphy/k7ddrphy.py rename to misoclib/sdram/phy/k7ddrphy.py index f6012940b..5e83f161a 100644 --- a/misoclib/sdramphy/k7ddrphy.py +++ b/misoclib/sdram/phy/k7ddrphy.py @@ -4,7 +4,7 @@ from migen.fhdl.std import * from migen.bus.dfi import * from migen.bank.description import * -from misoclib import lasmicon +from misoclib import sdram class K7DDRPHY(Module, AutoCSR): def __init__(self, pads, memtype): @@ -24,7 +24,7 @@ class K7DDRPHY(Module, AutoCSR): self._r_wdly_dqs_rst = CSR() self._r_wdly_dqs_inc = CSR() - self.phy_settings = lasmicon.PhySettings( + self.phy_settings = sdram.PhySettings( memtype=memtype, dfi_d=2*d, nphases=nphases, diff --git a/misoclib/sdramphy/s6ddrphy.py b/misoclib/sdram/phy/s6ddrphy.py similarity index 99% rename from misoclib/sdramphy/s6ddrphy.py rename to misoclib/sdram/phy/s6ddrphy.py index 9c5c92580..0dd383726 100644 --- a/misoclib/sdramphy/s6ddrphy.py +++ b/misoclib/sdram/phy/s6ddrphy.py @@ -18,7 +18,7 @@ from migen.fhdl.std import * from migen.bus.dfi import * from migen.genlib.record import * -from misoclib import lasmicon +from misoclib import sdram class S6DDRPHY(Module): def __init__(self, pads, memtype, rd_bitslip, wr_bitslip, dqs_ddr_alignment): @@ -29,7 +29,7 @@ class S6DDRPHY(Module): d = flen(pads.dq) nphases = 2 - self.phy_settings = lasmicon.PhySettings( + self.phy_settings = sdram.PhySettings( memtype=memtype, dfi_d=2*d, nphases=nphases, diff --git a/targets/kc705.py b/targets/kc705.py index cd0df7696..2bab721ec 100644 --- a/targets/kc705.py +++ b/targets/kc705.py @@ -1,8 +1,8 @@ from migen.fhdl.std import * from migen.genlib.resetsync import AsyncResetSynchronizer -from misoclib import lasmicon, spiflash, ethmac -from misoclib.sdramphy import k7ddrphy +from misoclib import sdram, spiflash, ethmac +from misoclib.sdram.phy import k7ddrphy from misoclib.gensoc import SDRAMSoC from misoclib.ethmac.phy import gmii @@ -75,12 +75,12 @@ class BaseSoC(SDRAMSoC): self.submodules.crg = _CRG(platform) - sdram_geom = lasmicon.GeomSettings( + sdram_geom = sdram.GeomSettings( bank_a=3, row_a=16, col_a=10 ) - sdram_timing = lasmicon.TimingSettings( + sdram_timing = sdram.TimingSettings( tRP=self.ns(15), tRCD=self.ns(15), tWR=self.ns(15), diff --git a/targets/mlabs_video.py b/targets/mlabs_video.py index 869f232cd..fcc219a28 100644 --- a/targets/mlabs_video.py +++ b/targets/mlabs_video.py @@ -4,8 +4,8 @@ from fractions import Fraction from migen.fhdl.std import * from mibuild.generic_platform import ConstraintError -from misoclib import lasmicon, mxcrg, norflash16, ethmac, framebuffer, gpio -from misoclib.sdramphy import s6ddrphy +from misoclib import sdram, mxcrg, norflash16, minimac3, framebuffer, gpio +from misoclib.sdram.phy import s6ddrphy from misoclib.gensoc import SDRAMSoC from misoclib.ethmac.phy import mii @@ -31,12 +31,12 @@ class BaseSoC(SDRAMSoC): cpu_reset_address=0x00180000, **kwargs) - sdram_geom = lasmicon.GeomSettings( + sdram_geom = sdram.GeomSettings( bank_a=2, row_a=13, col_a=10 ) - sdram_timing = lasmicon.TimingSettings( + sdram_timing = sdram.TimingSettings( tRP=self.ns(15), tRCD=self.ns(15), tWR=self.ns(15), diff --git a/targets/ppro.py b/targets/ppro.py index 05bfea3bb..34b1a6381 100644 --- a/targets/ppro.py +++ b/targets/ppro.py @@ -3,8 +3,8 @@ from fractions import Fraction from migen.fhdl.std import * from migen.genlib.resetsync import AsyncResetSynchronizer -from misoclib import lasmicon, spiflash -from misoclib.sdramphy import gensdrphy +from misoclib import spiflash, sdram +from misoclib.sdram.phy import gensdrphy from misoclib.gensoc import SDRAMSoC class _CRG(Module): @@ -67,12 +67,12 @@ class BaseSoC(SDRAMSoC): self.submodules.crg = _CRG(platform, clk_freq) - sdram_geom = lasmicon.GeomSettings( + sdram_geom = sdram.GeomSettings( bank_a=2, row_a=12, col_a=8 ) - sdram_timing = lasmicon.TimingSettings( + sdram_timing = sdram.TimingSettings( tRP=self.ns(15), tRCD=self.ns(15), tWR=self.ns(14),