From d021564fca8ac6d239dad2b18b5531cc9ee249c6 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 27 Oct 2023 15:24:57 +0200 Subject: [PATCH] interconnect/wishbone: Revert SRAM to Module, needs to be investigated. --- litex/soc/interconnect/wishbone.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex/soc/interconnect/wishbone.py b/litex/soc/interconnect/wishbone.py index 5b4323ef5..084930418 100644 --- a/litex/soc/interconnect/wishbone.py +++ b/litex/soc/interconnect/wishbone.py @@ -392,7 +392,7 @@ class Converter(LiteXModule): # Wishbone SRAM ------------------------------------------------------------------------------------ -class SRAM(LiteXModule): +class SRAM(Module): # FIXME: Switch to LiteXModule. def __init__(self, mem_or_size, read_only=None, write_only=None, init=None, bus=None, name=None): if bus is None: bus = Interface(data_width=32, address_width=32, addressing="word")