From d05fe673a0ea979a24773600616d31895ba0ef56 Mon Sep 17 00:00:00 2001
From: "William D. Jones" <thor0505@comcast.net>
Date: Mon, 29 Oct 2018 00:59:13 -0400
Subject: [PATCH] cpu/picorv32: Extract picorv32 parameters from Instance
 constructor to facilitate creating variant CPUs.

---
 litex/soc/cores/cpu/picorv32/core.py | 54 ++++++++++++++++------------
 1 file changed, 31 insertions(+), 23 deletions(-)

diff --git a/litex/soc/cores/cpu/picorv32/core.py b/litex/soc/cores/cpu/picorv32/core.py
index 7fe830d66..349cfe103 100644
--- a/litex/soc/cores/cpu/picorv32/core.py
+++ b/litex/soc/cores/cpu/picorv32/core.py
@@ -29,31 +29,39 @@ class PicoRV32(Module):
         mem_wstrb = Signal(4)
         mem_rdata = Signal(32)
 
+        # PicoRV32 parameters. To create a new variant, modify this dictionary
+        # and change the desired parameters.
+        picorv32_params = {
+            "p_ENABLE_COUNTERS" : 1,
+            "p_ENABLE_COUNTERS64" : 1,
+            # Changing REGS has no effect as on FPGAs, the registers are
+            # implemented using a register file stored in DPRAM.
+            "p_ENABLE_REGS_16_31" : 1,
+            "p_ENABLE_REGS_DUALPORT" : 1,
+            "p_LATCHED_MEM_RDATA" : 0,
+            "p_TWO_STAGE_SHIFT" : 1,
+            "p_TWO_CYCLE_COMPARE" : 0,
+            "p_TWO_CYCLE_ALU" : 0,
+            "p_CATCH_MISALIGN" : 1,
+            "p_CATCH_ILLINSN" : 1,
+            "p_ENABLE_PCPI" : 0,
+            "p_ENABLE_MUL" : 1,
+            "p_ENABLE_DIV" : 1,
+            "p_ENABLE_FAST_MUL" : 0,
+            "p_ENABLE_IRQ" : 1,
+            "p_ENABLE_IRQ_QREGS" : 1,
+            "p_ENABLE_IRQ_TIMER" : 1,
+            "p_ENABLE_TRACE" : 0,
+            "p_MASKED_IRQ" : 0x00000000,
+            "p_LATCHED_IRQ" : 0xffffffff,
+            "p_PROGADDR_RESET" : progaddr_reset,
+            "p_PROGADDR_IRQ" : 0x00000010,
+            "p_STACKADDR" : 0xffffffff
+        }
+
         self.specials += Instance("picorv32",
             # parameters
-            p_ENABLE_COUNTERS=1,
-            p_ENABLE_COUNTERS64=1,
-            p_ENABLE_REGS_16_31=1,
-            p_ENABLE_REGS_DUALPORT=1,
-            p_LATCHED_MEM_RDATA=0,
-            p_TWO_STAGE_SHIFT=1,
-            p_TWO_CYCLE_COMPARE=0,
-            p_TWO_CYCLE_ALU=0,
-            p_CATCH_MISALIGN=1,
-            p_CATCH_ILLINSN=1,
-            p_ENABLE_PCPI=0,
-            p_ENABLE_MUL=1,
-            p_ENABLE_DIV=1,
-            p_ENABLE_FAST_MUL=0,
-            p_ENABLE_IRQ=1,
-            p_ENABLE_IRQ_QREGS=1,
-            p_ENABLE_IRQ_TIMER=1,
-            p_ENABLE_TRACE=0,
-            p_MASKED_IRQ=0x00000000,
-            p_LATCHED_IRQ=0xffffffff,
-            p_PROGADDR_RESET=progaddr_reset,
-            p_PROGADDR_IRQ=0x00000010,
-            p_STACKADDR=0xffffffff,
+            **picorv32_params,
 
             # clock / reset
             i_clk=ClockSignal(),