From d0c4199096b4da074068be72a7547b3b6775f23c Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 18 Mar 2021 19:05:12 +0100 Subject: [PATCH] cores/gpio: Fix GPIOIRQ. Compilation tested in Arty with: from litex.soc.cores.gpio import GPIOIn self.submodules.gpio_in = GPIOIn(platform.request("user_sw", 0), with_irq=True) self.add_csr("gpio_in") self.add_interrupt("gpio_in") --- litex/soc/cores/gpio.py | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/litex/soc/cores/gpio.py b/litex/soc/cores/gpio.py index 5474a4ceb..12239f4c7 100644 --- a/litex/soc/cores/gpio.py +++ b/litex/soc/cores/gpio.py @@ -18,8 +18,8 @@ def _to_signal(obj): return obj.raw_bits() if isinstance(obj, Record) else obj -class _GPIOIRQ(Module, AutoCSR): - def __init__(self, in_pads): +class _GPIOIRQ: + def add_irq(self, in_pads): self._polarity = CSRStorage(len(in_pads), description="GPIO IRQ Polarity: 0: Rising Edge, 1: Falling Edge.") # # # @@ -32,13 +32,13 @@ class _GPIOIRQ(Module, AutoCSR): # GPIO Input --------------------------------------------------------------------------------------- -class GPIOIn(Module, AutoCSR): +class GPIOIn(_GPIOIRQ, Module, AutoCSR): def __init__(self, pads, with_irq=False): pads = _to_signal(pads) self._in = CSRStatus(len(pads), description="GPIO Input(s) Status.") self.specials += MultiReg(pads, self._in.status) if with_irq: - self.submodules.irq = _GPIOIRQ(self._in.status) + self.add_irq(self._in.status) # GPIO Output -------------------------------------------------------------------------------------- @@ -60,7 +60,7 @@ class GPIOInOut(Module): # GPIO Tristate ------------------------------------------------------------------------------------ -class GPIOTristate(Module, AutoCSR): +class GPIOTristate(_GPIOIRQ, Module, AutoCSR): def __init__(self, pads, with_irq=False): assert isinstance(pads, Signal) nbits = len(pads) @@ -78,4 +78,4 @@ class GPIOTristate(Module, AutoCSR): self.specials += MultiReg(t.i, self._in.status[i]) if with_irq: - self.submodules.irq = _GPIOIRQ(self._in.status) + self.add_irq(self._in.status)