From d0dc5c8d956e75d4fe975f1c620fc9f84cd549b3 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Thu, 17 Feb 2022 10:36:05 +0100
Subject: [PATCH] CHANGES: Update.

---
 CHANGES | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/CHANGES b/CHANGES
index aa507de2f..326207314 100644
--- a/CHANGES
+++ b/CHANGES
@@ -26,6 +26,10 @@
 	- cores/jtag:         Add initial JTAG-UART/JTAGBone Altera/Intel support.
 	- LiteScope:          Add Samplerate support.
 	- cores/bitbang:      Add optional I2C initialization by CPU.
+	- libliteeth/tftp:    Add blocksize support an increase to 1024 bytes (allow 64MB filesize).
+	- soc/add_sdram:      Make AXI integration more flexible (remove some specific Rocket hardcoding).
+	- cpu/neorv32:        Add initial support (RV32I, VHDL converted to Verilog through GHDL-Yosys-synth).
+	- cpu/naxriscv:       Add initial support (RV32IMA, already able to run Linux).
 
     [> API changes/Deprecation
 	--------------------------