From d0edb7e2b8cc08c9d9f73d01abc2413c76a46d4b Mon Sep 17 00:00:00 2001
From: Sebastien Bourdeauducq <sebastien@milkymist.org>
Date: Sun, 8 Sep 2013 12:55:26 +0200
Subject: [PATCH] dvisampler: reset PLL at startup

---
 milkymist/dvisampler/clocking.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/milkymist/dvisampler/clocking.py b/milkymist/dvisampler/clocking.py
index bf6f01e85..9e261d05c 100644
--- a/milkymist/dvisampler/clocking.py
+++ b/milkymist/dvisampler/clocking.py
@@ -4,7 +4,7 @@ from migen.bank.description import *
 
 class Clocking(Module, AutoCSR):
 	def __init__(self, pads):
-		self._r_pll_reset = CSRStorage()
+		self._r_pll_reset = CSRStorage(reset=1)
 		self._r_locked = CSRStatus()
 
 		self.locked = Signal()