From d32e393033e2682b678bef225fc91be389544a13 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 23 Nov 2018 18:33:53 +0100 Subject: [PATCH] soc/cores/spi_flash: add missing endianness parameter --- litex/soc/cores/spi_flash.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex/soc/cores/spi_flash.py b/litex/soc/cores/spi_flash.py index 86cab3ee1..35d2ac447 100644 --- a/litex/soc/cores/spi_flash.py +++ b/litex/soc/cores/spi_flash.py @@ -117,7 +117,7 @@ class SpiFlashDualQuad(Module, AutoCSR): class SpiFlashSingle(Module, AutoCSR): - def __init__(self, pads, dummy=15, div=2): + def __init__(self, pads, dummy=15, div=2, endianness="big"): """ Simple SPI flash. Supports 1-bit reads. Only supports mode0 (cpol=0, cpha=0).