From 92c8f7dc7cabbc3de4c62880c8e2ceb84c720d92 Mon Sep 17 00:00:00 2001 From: Marek Materzok Date: Tue, 21 Dec 2021 18:10:12 +0100 Subject: [PATCH] Fix typo jtabone -> jtagbone --- litex/soc/integration/soc.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py index 07ee6485d..d074aa596 100644 --- a/litex/soc/integration/soc.py +++ b/litex/soc/integration/soc.py @@ -1242,7 +1242,7 @@ class LiteXSoC(SoC): def add_jtagbone(self, chain=1): from litex.soc.cores import uart from litex.soc.cores.jtag import JTAGPHY - self.check_if_exists("jtabone") + self.check_if_exists("jtagbone") self.submodules.jtagbone_phy = JTAGPHY(device=self.platform.device, chain=chain) self.submodules.jtagbone = uart.UARTBone(phy=self.jtagbone_phy, clk_freq=self.sys_clk_freq) self.bus.add_master(name="jtagbone", master=self.jtagbone.wishbone)