From d36f98bf45c20e2f1895abd4aadf528bf129db11 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 15 Sep 2022 15:52:03 +0200 Subject: [PATCH] axi/axi_full: Simplify by switching AXI channels to AXIStreamInterface. --- litex/soc/interconnect/axi/axi_full.py | 76 ++++++++++--------- .../interconnect/axi/axi_full_to_axi_lite.py | 7 +- test/test_axi.py | 6 +- 3 files changed, 49 insertions(+), 40 deletions(-) diff --git a/litex/soc/interconnect/axi/axi_full.py b/litex/soc/interconnect/axi/axi_full.py index eed496363..34946f468 100644 --- a/litex/soc/interconnect/axi/axi_full.py +++ b/litex/soc/interconnect/axi/axi_full.py @@ -15,12 +15,13 @@ from litex.soc.interconnect import stream from litex.build.generic_platform import * from litex.soc.interconnect.axi.axi_common import * +from litex.soc.interconnect.axi.axi_stream import AXIStreamInterface # AXI Definition ----------------------------------------------------------------------------------- -def ax_description(address_width, id_width=0, user_width=0): +def ax_description(address_width): # * present for interconnect with others cores but not used by LiteX. - ax = [ + return [ ("addr", address_width), # Address Width. ("burst", 2), # Burst type. ("len", 8), # Number of data (-1) transfers (up to 256). @@ -31,41 +32,21 @@ def ax_description(address_width, id_width=0, user_width=0): ("qos", 4), # * ("region", 4), # * ] - if id_width: - ax += [("id", id_width)] # ID Width. - if user_width: - ax += [("user", user_width)] # * - return ax -def w_description(data_width, id_width=0, user_width=0): - w = [ +def w_description(data_width): + return [ ("data", data_width), ("strb", data_width//8), ] - if id_width: - w += [("id", id_width)] - if user_width: - w += [("user", user_width)] - return w -def b_description(id_width=0, user_width=0): - b = [("resp", 2)] - if id_width: - b += [("id", id_width)] - if user_width: - b += [("user", user_width)] - return b +def b_description(): + return [("resp", 2)] -def r_description(data_width, id_width=0, user_width=0): - r = [ +def r_description(data_width): + return [ ("resp", 2), ("data", data_width), ] - if id_width: - r += [("id", id_width)] - if user_width: - r += [("user", user_width)] - return r class AXIInterface: def __init__(self, data_width=32, address_width=32, id_width=1, clock_domain="sys", name=None, bursting=False, @@ -73,18 +54,45 @@ class AXIInterface: w_user_width = 0, b_user_width = 0, ar_user_width = 0, - r_user_width = 0): + r_user_width = 0 + ): + # Parameters. self.data_width = data_width self.address_width = address_width self.id_width = id_width self.clock_domain = clock_domain self.bursting = bursting # FIXME: Use or add check. - self.aw = stream.Endpoint(ax_description(address_width, id_width, aw_user_width), name=name) - self.w = stream.Endpoint(w_description(data_width, id_width, w_user_width), name=name) - self.b = stream.Endpoint(b_description(id_width, b_user_width), name=name) - self.ar = stream.Endpoint(ax_description(address_width, id_width, ar_user_width), name=name) - self.r = stream.Endpoint(r_description(data_width, id_width, r_user_width), name=name) + # Write Channels. + # --------------- + self.aw = AXIStreamInterface(name=name, + layout = ax_description(address_width), + id_width = id_width, + user_width = aw_user_width + ) + self.w = AXIStreamInterface(name=name, + layout = w_description(data_width), + id_width = id_width, + user_width = w_user_width + ) + self.b = AXIStreamInterface(name=name, + layout = b_description(), + id_width = id_width, + user_width = b_user_width + ) + + # Read Channels. + # -------------- + self.ar = AXIStreamInterface(name=name, + layout = ax_description(address_width), + id_width = id_width, + user_width = ar_user_width + ) + self.r = AXIStreamInterface(name=name, + layout = r_description(data_width), + id_width = id_width, + user_width = r_user_width + ) def connect_to_pads(self, pads, mode="master"): return connect_to_pads(self, pads, mode, axi_full=True) diff --git a/litex/soc/interconnect/axi/axi_full_to_axi_lite.py b/litex/soc/interconnect/axi/axi_full_to_axi_lite.py index 8468b8b88..6bb03d5ba 100644 --- a/litex/soc/interconnect/axi/axi_full_to_axi_lite.py +++ b/litex/soc/interconnect/axi/axi_full_to_axi_lite.py @@ -25,9 +25,10 @@ class AXI2AXILite(Module): assert axi.data_width == axi_lite.data_width assert axi.address_width == axi_lite.address_width - ax_buffer = stream.Buffer(ax_description(axi.address_width, axi.id_width)) - ax_burst = stream.Endpoint(ax_description(axi.address_width, axi.id_width)) - ax_beat = stream.Endpoint(ax_description(axi.address_width, axi.id_width)) + ax_burst = AXIStreamInterface(layout=ax_description(axi.address_width), id_width=axi.id_width) + ax_beat = AXIStreamInterface(layout=ax_description(axi.address_width), id_width=axi.id_width) + ax_buffer = stream.Buffer(ax_burst.description) + self.comb += ax_burst.connect(ax_buffer.sink) ax_burst2beat = AXIBurst2Beat(ax_buffer.source, ax_beat) self.submodules += ax_buffer, ax_burst2beat diff --git a/test/test_axi.py b/test/test_axi.py index ff2da770e..ee53199dd 100644 --- a/test/test_axi.py +++ b/test/test_axi.py @@ -96,9 +96,9 @@ class TestAXI(unittest.TestCase): yield # DUT - ax_burst = stream.Endpoint(ax_description(32, 32)) - ax_beat = stream.Endpoint(ax_description(32, 32)) - dut = AXIBurst2Beat(ax_burst, ax_beat) + ax_burst = AXIStreamInterface(layout=ax_description(32), id_width=32) + ax_beat = AXIStreamInterface(layout=ax_description(32), id_width=32) + dut = AXIBurst2Beat(ax_burst, ax_beat) # Generate DUT input (bursts). prng = random.Random(42)