diff --git a/litex/build/sim/core/Makefile b/litex/build/sim/core/Makefile
index 0388cdda0..782ac46b3 100644
--- a/litex/build/sim/core/Makefile
+++ b/litex/build/sim/core/Makefile
@@ -24,7 +24,7 @@ $(OBJS_SIM): %.o: $(SRC_DIR)/%.c
 
 .PHONY: sim
 sim: mkdir $(OBJS_SIM)
-	verilator -Wno-fatal -O3 --cc dut.v --exe \
+	verilator -Wno-fatal -O3 --cc dut.v --top-module dut --exe \
 		$(SRCS_SIM_CPP) $(OBJS_SIM) \
 		-CFLAGS "$(CFLAGS) -I$(SRC_DIR)" \
 		-LDFLAGS "$(LDFLAGS)" \
diff --git a/litex/build/sim/verilator.py b/litex/build/sim/verilator.py
index 312d51e3f..a2e39b47a 100644
--- a/litex/build/sim/verilator.py
+++ b/litex/build/sim/verilator.py
@@ -136,7 +136,7 @@ sudo obj_dir/Vdut
 
 
 class SimVerilatorToolchain:
-    def build(self, platform, fragment, build_dir="build", build_name="top",
+    def build(self, platform, fragment, build_dir="build", build_name="dut",
             toolchain_path=None, serial="console", run=True, verbose=True,
             sim_config=None):
         os.makedirs(build_dir, exist_ok=True)
@@ -146,9 +146,9 @@ class SimVerilatorToolchain:
             fragment = fragment.get_fragment()
         platform.finalize(fragment)
 
-        v_output = platform.get_verilog(fragment)
+        v_output = platform.get_verilog(fragment, name=build_name)
         named_sc, named_pc = platform.resolve_signals(v_output.ns)
-        v_output.write("dut.v")
+        v_output.write(build_name + ".v")
 
         include_paths = []
         for source in platform.sources: