From d4c1a1081763204f271e4a4755522f6b27a327dd Mon Sep 17 00:00:00 2001
From: Dolu1990 <charles.papon.90@gmail.com>
Date: Tue, 14 May 2024 14:57:29 +0200
Subject: [PATCH] cores/cpu/naxriscv: Add baremetal IRQ support

---
 litex/soc/cores/cpu/naxriscv/core.py |  2 +-
 litex/soc/cores/cpu/naxriscv/crt0.S  |  6 ++++--
 litex/soc/cores/cpu/naxriscv/irq.h   | 22 ++++++++++++++++------
 3 files changed, 21 insertions(+), 9 deletions(-)

diff --git a/litex/soc/cores/cpu/naxriscv/core.py b/litex/soc/cores/cpu/naxriscv/core.py
index a686534c9..7d8da8fb9 100755
--- a/litex/soc/cores/cpu/naxriscv/core.py
+++ b/litex/soc/cores/cpu/naxriscv/core.py
@@ -93,7 +93,7 @@ class NaxRiscv(CPU):
     def gcc_flags(self):
         flags =  f" -march={NaxRiscv.get_arch()} -mabi={NaxRiscv.get_abi()}"
         flags += f" -D__NaxRiscv__"
-        flags += f" -DUART_POLLING"
+        flags += f" -D__riscv_plic__"
         return flags
 
     # Reserved Interrupts.
diff --git a/litex/soc/cores/cpu/naxriscv/crt0.S b/litex/soc/cores/cpu/naxriscv/crt0.S
index b27df7f47..4c4c69765 100644
--- a/litex/soc/cores/cpu/naxriscv/crt0.S
+++ b/litex/soc/cores/cpu/naxriscv/crt0.S
@@ -113,8 +113,10 @@ bss_loop:
   j bss_loop
 bss_done:
 
-  li a0, 0x880  //880 enable timer + external interrupt sources (until mstatus.MIE is set, they will never trigger an interrupt)
-  csrw mie,a0
+  call plic_init // initialize external interrupt controller
+  li t0, 0x800   // external interrupt sources only (using LiteX timer);
+                 // NOTE: must still enable mstatus.MIE!
+  csrw mie,t0
 
   call main
 infinit_loop:
diff --git a/litex/soc/cores/cpu/naxriscv/irq.h b/litex/soc/cores/cpu/naxriscv/irq.h
index 558adc4f1..a8325ec46 100644
--- a/litex/soc/cores/cpu/naxriscv/irq.h
+++ b/litex/soc/cores/cpu/naxriscv/irq.h
@@ -9,30 +9,40 @@ extern "C" {
 #include <generated/csr.h>
 #include <generated/soc.h>
 
+// NaxRiscv uses a Platform-Level Interrupt Controller (PLIC) which
+// is programmed and queried via a set of MMIO registerss
+
+#define PLIC_BASE    0xf0c00000L // Base address and per-pin priority array
+#define PLIC_PENDING 0xf0c01000L // Bit field matching currently pending pins
+#define PLIC_ENABLED 0xf0c02000L // Bit field corresponding to the current mask
+#define PLIC_THRSHLD 0xf0e00000L // Per-pin priority must be >= this to trigger
+#define PLIC_CLAIM   0xf0e00004L // Claim & completion register address
+
+#define PLIC_EXT_IRQ_BASE 0
+
 static inline unsigned int irq_getie(void)
 {
-	return 0;
+	return (csrr(mstatus) & CSR_MSTATUS_MIE) != 0;
 }
 
 static inline void irq_setie(unsigned int ie)
 {
-
+	if(ie) csrs(mstatus,CSR_MSTATUS_MIE); else csrc(mstatus,CSR_MSTATUS_MIE);
 }
 
 static inline unsigned int irq_getmask(void)
 {
-
-	return 0;
+	return *((unsigned int *)PLIC_ENABLED) >> PLIC_EXT_IRQ_BASE;
 }
 
 static inline void irq_setmask(unsigned int mask)
 {
-
+	*((unsigned int *)PLIC_ENABLED) = mask << PLIC_EXT_IRQ_BASE;
 }
 
 static inline unsigned int irq_pending(void)
 {
-	return 0;
+	return *((unsigned int *)PLIC_PENDING) >> PLIC_EXT_IRQ_BASE;
 }
 
 #ifdef __cplusplus