diff --git a/litex/soc/cores/cpu/vexriscv_smp/core.py b/litex/soc/cores/cpu/vexriscv_smp/core.py
index 758f6b16d..6ed881511 100644
--- a/litex/soc/cores/cpu/vexriscv_smp/core.py
+++ b/litex/soc/cores/cpu/vexriscv_smp/core.py
@@ -44,13 +44,15 @@ class VexRiscvSMP(CPU):
 
     @staticmethod
     def args_fill(parser):
-        parser.add_argument("--cpu-count",    default=1,    help="")
-        parser.add_argument("--dcache-width", default=None, help="L1 data cache bus width")
-        parser.add_argument("--icache-width", default=None, help="L1 instruction cache bus width")
-        parser.add_argument("--dcache-size",  default=None, help="L1 data cache size in byte per CPU")
-        parser.add_argument("--dcache-ways",  default=None, help="L1 data cache ways per CPU")
-        parser.add_argument("--icache-size",  default=None, help="L1 instruction cache size in byte per CPU")
-        parser.add_argument("--icache-ways",  default=None, help="L1 instruction cache ways per CPU")
+        parser.add_argument("--cpu-count",            default=1,           help="")
+        parser.add_argument("--with-coherent-dma",    action='store_true', help="")
+        parser.add_argument("--without-coherent-dma", action='store_true', help="")
+        parser.add_argument("--dcache-width",         default=None,        help="L1 data cache bus width")
+        parser.add_argument("--icache-width",         default=None,        help="L1 instruction cache bus width")
+        parser.add_argument("--dcache-size",          default=None,        help="L1 data cache size in byte per CPU")
+        parser.add_argument("--dcache-ways",          default=None,        help="L1 data cache ways per CPU")
+        parser.add_argument("--icache-size",          default=None,        help="L1 instruction cache size in byte per CPU")
+        parser.add_argument("--icache-ways",          default=None,        help="L1 instruction cache ways per CPU")
 
 
     @staticmethod
@@ -64,6 +66,8 @@ class VexRiscvSMP(CPU):
             VexRiscvSMP.dcache_ways  = 2
             VexRiscvSMP.icache_ways  = 2
             VexRiscvSMP.coherent_dma = True
+        if(args.with_coherent_dma): VexRiscvSMP.coherent_dma    = bool(True)
+        if(args.without_coherent_dma): VexRiscvSMP.coherent_dma = bool(False)
         if(args.dcache_width): VexRiscvSMP.dcache_width = int(args.dcache_width)
         if(args.icache_width): VexRiscvSMP.icache_width = int(args.icache_width)
         if(args.icache_width): VexRiscvSMP.dcache_size  = int(args.dcache_size)