From d51d33af7373c82935de08e3e373588357063b0e Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Sat, 14 Feb 2015 03:05:07 -0800 Subject: [PATCH] mibuild: make resolve_signals public --- mibuild/altera_quartus.py | 2 +- mibuild/generic_platform.py | 2 +- mibuild/xilinx_ise.py | 4 ++-- mibuild/xilinx_vivado.py | 2 +- 4 files changed, 5 insertions(+), 5 deletions(-) diff --git a/mibuild/altera_quartus.py b/mibuild/altera_quartus.py index 6939eb67d..348596a51 100644 --- a/mibuild/altera_quartus.py +++ b/mibuild/altera_quartus.py @@ -81,7 +81,7 @@ class AlteraQuartusPlatform(GenericPlatform): self.finalize(fragment) v_src, vns = self.get_verilog(fragment) - named_sc, named_pc = self._resolve_signals(vns) + named_sc, named_pc = self.resolve_signals(vns) v_file = build_name + ".v" tools.write_to_file(v_file, v_src) sources = self.sources + [(v_file, "verilog")] diff --git a/mibuild/generic_platform.py b/mibuild/generic_platform.py index 6bdcbebc1..b57ba59bf 100644 --- a/mibuild/generic_platform.py +++ b/mibuild/generic_platform.py @@ -240,7 +240,7 @@ class GenericPlatform: def add_verilog_include_path(self, path): self.verilog_include_paths.append(os.path.abspath(path)) - def _resolve_signals(self, vns): + def resolve_signals(self, vns): # resolve signal names in constraints sc = self.constraint_manager.get_sig_constraints() named_sc = [(vns.get_name(sig), pins, others, resource) for sig, pins, others, resource in sc] diff --git a/mibuild/xilinx_ise.py b/mibuild/xilinx_ise.py index d681fbe52..d291f72f0 100644 --- a/mibuild/xilinx_ise.py +++ b/mibuild/xilinx_ise.py @@ -144,7 +144,7 @@ class XilinxISEPlatform(xilinx_common.XilinxGenericPlatform): if mode == "xst" or mode == "yosys": v_src, vns = self.get_verilog(fragment) - named_sc, named_pc = self._resolve_signals(vns) + named_sc, named_pc = self.resolve_signals(vns) v_file = build_name + ".v" tools.write_to_file(v_file, v_src) sources = self.sources + [(v_file, "verilog")] @@ -162,7 +162,7 @@ class XilinxISEPlatform(xilinx_common.XilinxGenericPlatform): if mode == "edif" or mode == "mist": e_src, vns = self.get_edif(fragment) - named_sc, named_pc = self._resolve_signals(vns) + named_sc, named_pc = self.resolve_signals(vns) e_file = build_name + ".edif" tools.write_to_file(e_file, e_src) isemode = "edif" diff --git a/mibuild/xilinx_vivado.py b/mibuild/xilinx_vivado.py index afeb68171..d55c930e1 100644 --- a/mibuild/xilinx_vivado.py +++ b/mibuild/xilinx_vivado.py @@ -103,7 +103,7 @@ class XilinxVivadoPlatform(xilinx_common.XilinxGenericPlatform): fragment = fragment.get_fragment() self.finalize(fragment) v_src, vns = self.get_verilog(fragment) - named_sc, named_pc = self._resolve_signals(vns) + named_sc, named_pc = self.resolve_signals(vns) v_file = build_name + ".v" tools.write_to_file(v_file, v_src) sources = self.sources + [(v_file, "verilog")]