diff --git a/misoc/interconnect/wishbone.py b/misoc/interconnect/wishbone.py
index 990908ddc..d24148beb 100644
--- a/misoc/interconnect/wishbone.py
+++ b/misoc/interconnect/wishbone.py
@@ -641,7 +641,7 @@ class CSRBank(csr.GenericBank):
 
         ###
 
-        GenericBank.__init__(self, description, len(self.bus.dat_w))
+        csr.GenericBank.__init__(self, description, len(self.bus.dat_w))
 
         for i, c in enumerate(self.simple_csrs):
             self.comb += [