From d554a06eba49bfc096d38c8d51fc354c7e21cfa6 Mon Sep 17 00:00:00 2001
From: Sebastien Bourdeauducq <sb@m-labs.hk>
Date: Tue, 3 Nov 2015 18:45:23 +0800
Subject: [PATCH] interconnect/wishbone: fix CSRBank init

---
 misoc/interconnect/wishbone.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/misoc/interconnect/wishbone.py b/misoc/interconnect/wishbone.py
index 990908ddc..d24148beb 100644
--- a/misoc/interconnect/wishbone.py
+++ b/misoc/interconnect/wishbone.py
@@ -641,7 +641,7 @@ class CSRBank(csr.GenericBank):
 
         ###
 
-        GenericBank.__init__(self, description, len(self.bus.dat_w))
+        csr.GenericBank.__init__(self, description, len(self.bus.dat_w))
 
         for i, c in enumerate(self.simple_csrs):
             self.comb += [