From d69b4443b32d491ba80811ae885849fed58223d0 Mon Sep 17 00:00:00 2001 From: David Sawatzke Date: Thu, 9 Apr 2020 05:36:10 +0200 Subject: [PATCH] Add riscv64-none-elf triple --- litex/soc/cores/cpu/blackparrot/core.py | 3 ++- litex/soc/cores/cpu/minerva/core.py | 2 +- litex/soc/cores/cpu/picorv32/core.py | 2 +- litex/soc/cores/cpu/rocket/core.py | 3 ++- litex/soc/cores/cpu/vexriscv/core.py | 2 +- 5 files changed, 7 insertions(+), 5 deletions(-) diff --git a/litex/soc/cores/cpu/blackparrot/core.py b/litex/soc/cores/cpu/blackparrot/core.py index b58ac1a1d..897664892 100644 --- a/litex/soc/cores/cpu/blackparrot/core.py +++ b/litex/soc/cores/cpu/blackparrot/core.py @@ -48,7 +48,8 @@ class BlackParrotRV64(CPU): name = "blackparrot" data_width = 64 endianness = "little" - gcc_triple = ("riscv64-unknown-elf", "riscv64-linux", "riscv-sifive-elf") + gcc_triple = ("riscv64-unknown-elf", "riscv64-linux", "riscv-sifive-elf", + "riscv64-none-elf") linker_output_format = "elf64-littleriscv" io_regions = {0x30000000: 0x20000000} # origin, length diff --git a/litex/soc/cores/cpu/minerva/core.py b/litex/soc/cores/cpu/minerva/core.py index 2c3d967cb..2edbfe7ee 100644 --- a/litex/soc/cores/cpu/minerva/core.py +++ b/litex/soc/cores/cpu/minerva/core.py @@ -18,7 +18,7 @@ class Minerva(CPU): data_width = 32 endianness = "little" gcc_triple = ("riscv64-unknown-elf", "riscv32-unknown-elf", "riscv-none-embed", - "riscv64-linux", "riscv-sifive-elf") + "riscv64-linux", "riscv-sifive-elf", "riscv64-none-elf") linker_output_format = "elf32-littleriscv" io_regions = {0x80000000: 0x80000000} # origin, length diff --git a/litex/soc/cores/cpu/picorv32/core.py b/litex/soc/cores/cpu/picorv32/core.py index c918b6d10..304f6c14d 100644 --- a/litex/soc/cores/cpu/picorv32/core.py +++ b/litex/soc/cores/cpu/picorv32/core.py @@ -35,7 +35,7 @@ class PicoRV32(CPU): data_width = 32 endianness = "little" gcc_triple = ("riscv64-unknown-elf", "riscv32-unknown-elf", "riscv-none-embed", - "riscv64-linux", "riscv-sifive-elf") + "riscv64-linux", "riscv-sifive-elf", "riscv64-none-elf") linker_output_format = "elf32-littleriscv" io_regions = {0x80000000: 0x80000000} # origin, length diff --git a/litex/soc/cores/cpu/rocket/core.py b/litex/soc/cores/cpu/rocket/core.py index 3f94cf2df..14bab0f41 100644 --- a/litex/soc/cores/cpu/rocket/core.py +++ b/litex/soc/cores/cpu/rocket/core.py @@ -67,7 +67,8 @@ class RocketRV64(CPU): name = "rocket" data_width = 64 endianness = "little" - gcc_triple = ("riscv64-unknown-elf", "riscv64-linux", "riscv-sifive-elf") + gcc_triple = ("riscv64-unknown-elf", "riscv64-linux", "riscv-sifive-elf", + "riscv64-none-elf") linker_output_format = "elf64-littleriscv" io_regions = {0x10000000: 0x70000000} # origin, length diff --git a/litex/soc/cores/cpu/vexriscv/core.py b/litex/soc/cores/cpu/vexriscv/core.py index 7c85a3c99..4e0bbc0a0 100644 --- a/litex/soc/cores/cpu/vexriscv/core.py +++ b/litex/soc/cores/cpu/vexriscv/core.py @@ -78,7 +78,7 @@ class VexRiscv(CPU, AutoCSR): data_width = 32 endianness = "little" gcc_triple = ("riscv64-unknown-elf", "riscv32-unknown-elf", "riscv-none-embed", - "riscv64-linux", "riscv-sifive-elf") + "riscv64-linux", "riscv-sifive-elf", "riscv64-none-elf") linker_output_format = "elf32-littleriscv" io_regions = {0x80000000: 0x80000000} # origin, length