From d6db2be6b63075268502ea36392b1f1bd517fc00 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Tue, 14 Mar 2023 11:17:14 +0100
Subject: [PATCH] software/liblitedram: Halve seed_array (Calibration was too
 long on US(+) devices) and fix write latency calibration presentation when
 SDRAM_DELAY_PER_DQ is not set.

---
 litex/soc/software/liblitedram/sdram.c | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/litex/soc/software/liblitedram/sdram.c b/litex/soc/software/liblitedram/sdram.c
index 06d01c35e..51805d11e 100644
--- a/litex/soc/software/liblitedram/sdram.c
+++ b/litex/soc/software/liblitedram/sdram.c
@@ -410,7 +410,7 @@ static unsigned int sdram_write_read_check_test_pattern(int module, unsigned int
 	return errors;
 }
 
-static int _seed_array[] = {42, 84, 36, 72, 24, 48};
+static int _seed_array[] = {42, 84, 36};
 static int _seed_array_length = sizeof(_seed_array) / sizeof(_seed_array[0]);
 
 static int run_test_pattern(int module, int dq_line) {
@@ -1028,9 +1028,15 @@ static void sdram_write_latency_calibration(void) {
 			for (i=0; i<bitslip; i++) {
 				sdram_leveling_action(module, dq_line, write_inc_dq_bitslip);
 			}
-		}
+#ifdef SDRAM_DELAY_PER_DQ
 		printf("\n");
+#endif
+		}
 	}
+#ifndef SDRAM_DELAY_PER_DQ
+	printf("\n");
+#endif
+
 }
 
 #endif // SDRAM_PHY_WRITE_LATENCY_CALIBRATION_CAPABLE