diff --git a/litex/soc/cores/uart.py b/litex/soc/cores/uart.py
index 9ee678761..eff637cad 100644
--- a/litex/soc/cores/uart.py
+++ b/litex/soc/cores/uart.py
@@ -46,7 +46,7 @@ class RS232ClkPhaseAccum(Module):
 
         # # #
 
-        phase = Signal(32)
+        phase = Signal(32, reset_less=True)
         self.sync += Cat(phase, self.tick).eq(tuning_word if mode == "tx" else 2**31)
         self.sync += If(self.enable, Cat(phase, self.tick).eq(phase + tuning_word))