From d6f24f2f68285b72d9345b5d25cb4cf56da3c87c Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Sun, 20 Jun 2021 14:33:25 +0200 Subject: [PATCH] cores/uart/RS232ClkPhaseAccum: Avoid reset on phase signal, improve timings/resources on iCE40. --- litex/soc/cores/uart.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex/soc/cores/uart.py b/litex/soc/cores/uart.py index 9ee678761..eff637cad 100644 --- a/litex/soc/cores/uart.py +++ b/litex/soc/cores/uart.py @@ -46,7 +46,7 @@ class RS232ClkPhaseAccum(Module): # # # - phase = Signal(32) + phase = Signal(32, reset_less=True) self.sync += Cat(phase, self.tick).eq(tuning_word if mode == "tx" else 2**31) self.sync += If(self.enable, Cat(phase, self.tick).eq(phase + tuning_word))