diff --git a/litex/tools/litex_sim.py b/litex/tools/litex_sim.py
index c8ef182b7..8bae6b6b3 100755
--- a/litex/tools/litex_sim.py
+++ b/litex/tools/litex_sim.py
@@ -124,6 +124,7 @@ class SimSoC(SoCSDRAM):
         # serial
         self.submodules.uart_phy = uart.RS232PHYModel(platform.request("serial"))
         self.submodules.uart = uart.UART(self.uart_phy)
+        self.add_csr("uart")
         self.add_interrupt("uart")
 
         # sdram