From 38b819c42a327b1f9f734c56cc4db5f18ab94ef5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?J=C4=99drzej=20Boczar?= Date: Wed, 23 Dec 2020 11:22:43 +0100 Subject: [PATCH] software/liblitedram: selectable write leveling MR (for LPDDR4 support) --- litex/soc/software/liblitedram/sdram.c | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/litex/soc/software/liblitedram/sdram.c b/litex/soc/software/liblitedram/sdram.c index 53e878974..3e72cc1ce 100644 --- a/litex/soc/software/liblitedram/sdram.c +++ b/litex/soc/software/liblitedram/sdram.c @@ -260,13 +260,14 @@ int _sdram_write_leveling_cdly_range_end = -1; static void sdram_write_leveling_on(void) { - sdram_dfii_pi0_address_write(DDRX_MR1 | (1 << 7)); - sdram_dfii_pi0_baddress_write(1); + // Flip write leveling bit in the Mode Register, as it is disabled by default + sdram_dfii_pi0_address_write(DDRX_MR_WRLVL_RESET ^ (1 << DDRX_MR_WRLVL_BIT)); + sdram_dfii_pi0_baddress_write(DDRX_MR_WRLVL_ADDRESS); command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS); #ifdef SDRAM_PHY_DDR4_RDIMM - sdram_dfii_pi0_address_write((DDRX_MR1 | (1 << 7)) ^ 0x2BF8) ; - sdram_dfii_pi0_baddress_write(1 ^ 0xF); + sdram_dfii_pi0_address_write((DDRX_MR_WRLVL_RESET ^ (1 << DDRX_MR_WRLVL_BIT)) ^ 0x2BF8) ; + sdram_dfii_pi0_baddress_write(DDRX_MR_WRLVL_ADDRESS ^ 0xF); command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS); #endif @@ -275,13 +276,13 @@ static void sdram_write_leveling_on(void) static void sdram_write_leveling_off(void) { - sdram_dfii_pi0_address_write(DDRX_MR1); - sdram_dfii_pi0_baddress_write(1); + sdram_dfii_pi0_address_write(DDRX_MR_WRLVL_RESET); + sdram_dfii_pi0_baddress_write(DDRX_MR_WRLVL_ADDRESS); command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS); #ifdef SDRAM_PHY_DDR4_RDIMM - sdram_dfii_pi0_address_write(DDRX_MR1 ^ 0x2BF8); - sdram_dfii_pi0_baddress_write(1 ^ 0xF); + sdram_dfii_pi0_address_write(DDRX_MR_WRLVL_RESET ^ 0x2BF8); + sdram_dfii_pi0_baddress_write(DDRX_MR_WRLVL_ADDRESS ^ 0xF); command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS); #endif