diff --git a/mibuild/altera/programmer.py b/mibuild/altera/programmer.py
index 13af0f492..e2e2cae50 100644
--- a/mibuild/altera/programmer.py
+++ b/mibuild/altera/programmer.py
@@ -7,5 +7,5 @@ class USBBlaster(GenericProgrammer):
     needs_bitreverse = False
 
     def load_bitstream(self, bitstream_file, port=0):
-        usb_port = "[USB-"+str(port)+"]"
-        subprocess.call(["quartus_pgm", "-m", "jtag", "-c", "USB-Blaster"+usb_port, "-o", "p;"+bitstream_file])
+        usb_port = "[USB-"+str(port) + "]"
+        subprocess.call(["quartus_pgm", "-m", "jtag", "-c", "USB-Blaster" + usb_port, "-o", "p;" + bitstream_file])
diff --git a/migen/bus/csr.py b/migen/bus/csr.py
index 7c1e6feeb..414363f9d 100644
--- a/migen/bus/csr.py
+++ b/migen/bus/csr.py
@@ -5,10 +5,10 @@ from migen.genlib.record import *
 from migen.genlib.misc import chooser
 
 _layout = [
-    ("adr",        "address_width",    DIR_M_TO_S),
-    ("we",        1,                    DIR_M_TO_S),
-    ("dat_w",    "data_width",        DIR_M_TO_S),
-    ("dat_r",    "data_width",        DIR_S_TO_M)
+    ("adr",  "address_width", DIR_M_TO_S),
+    ("we",                 1, DIR_M_TO_S),
+    ("dat_w",   "data_width", DIR_M_TO_S),
+    ("dat_r",   "data_width", DIR_S_TO_M)
 ]
 
 
diff --git a/migen/bus/wishbone.py b/migen/bus/wishbone.py
index 494da16bc..d4c24dd41 100644
--- a/migen/bus/wishbone.py
+++ b/migen/bus/wishbone.py
@@ -6,17 +6,17 @@ from migen.genlib.fsm import FSM, NextState
 from migen.bus.transactions import *
 
 _layout = [
-    ("adr",        30,                DIR_M_TO_S),
-    ("dat_w",    "data_width",     DIR_M_TO_S),
-    ("dat_r",    "data_width",     DIR_S_TO_M),
-    ("sel",        "sel_width",    DIR_M_TO_S),
-    ("cyc",        1,                DIR_M_TO_S),
-    ("stb",        1,                DIR_M_TO_S),
-    ("ack",        1,                DIR_S_TO_M),
-    ("we",        1,                DIR_M_TO_S),
-    ("cti",        3,                DIR_M_TO_S),
-    ("bte",        2,                DIR_M_TO_S),
-    ("err",        1,                DIR_S_TO_M)
+    ("adr",             30, DIR_M_TO_S),
+    ("dat_w", "data_width", DIR_M_TO_S),
+    ("dat_r", "data_width", DIR_S_TO_M),
+    ("sel",    "sel_width", DIR_M_TO_S),
+    ("cyc",              1, DIR_M_TO_S),
+    ("stb",              1, DIR_M_TO_S),
+    ("ack",              1, DIR_S_TO_M),
+    ("we",               1, DIR_M_TO_S),
+    ("cti",              3, DIR_M_TO_S),
+    ("bte",              2, DIR_M_TO_S),
+    ("err",              1, DIR_S_TO_M)
 ]