From d84ae7c80c4992329ecb871fbaf94e470424323b Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 19 Jan 2015 17:52:05 +0100 Subject: [PATCH] clean up --- Makefile | 29 ------------------ litesata/common.py | 6 ++++ litesata/phy/__init__.py | 8 ++--- litesata/phy/k7/crg.py | 4 +-- litesata/phy/k7/trx.py | 8 ++--- make.py | 47 ++++++++++++++++++++---------- targets/__init__.py | 0 targets/{bist_kc705.py => bist.py} | 7 +---- 8 files changed, 48 insertions(+), 61 deletions(-) delete mode 100644 Makefile create mode 100644 targets/__init__.py rename targets/{bist_kc705.py => bist.py} (97%) diff --git a/Makefile b/Makefile deleted file mode 100644 index 5a3406d1e..000000000 --- a/Makefile +++ /dev/null @@ -1,29 +0,0 @@ -MSCDIR = ../misoc -CURDIR = ../lite-sata -PYTHON = python3 -TOOLCHAIN = vivado -PROGRAMMER = vivado - -CMD = $(PYTHON) make.py -X $(CURDIR) -Op toolchain $(TOOLCHAIN) -Op programmer $(PROGRAMMER) -t bist_kc705 - -csv: - cd $(MSCDIR) && $(CMD) --csr_csv $(CURDIR)/test/csr.csv build-csr-csv -Ot export_mila True - cd $(CURDIR) - -bit: - cd $(MSCDIR) && $(CMD) build-bitstream - cd $(CURDIR) - -build: csv bit - -load: - cd $(MSCDIR) && $(CMD) load-bitstream - cd $(CURDIR) - -test: - cd test && $(PYTHON) test_regs.py - cd $(CURDIR) - -all: build load test - -.PHONY: load test all diff --git a/litesata/common.py b/litesata/common.py index 99c5d214b..90f7c23c4 100644 --- a/litesata/common.py +++ b/litesata/common.py @@ -13,6 +13,12 @@ from migen.actorlib.fifo import * from migen.actorlib.structuring import Pipeline, Converter # PHY / Link Layers +frequencies = { + "SATA3" : 150.0, + "SATA2" : 75.0, + "SATA1" : 37.5, +} + primitives = { "ALIGN" : 0x7B4A4ABC, "CONT" : 0X9999AA7C, diff --git a/litesata/phy/__init__.py b/litesata/phy/__init__.py index fcb206f37..58fb1f048 100644 --- a/litesata/phy/__init__.py +++ b/litesata/phy/__init__.py @@ -3,14 +3,14 @@ from litesata.phy.ctrl import * from litesata.phy.datapath import * class LiteSATAPHY(Module): - def __init__(self, device, pads, speed, clk_freq): - self.speed = speed + def __init__(self, device, pads, revision, clk_freq): + self.revision = revision # Transceiver / Clocks if device[:3] == "xc7": # Kintex 7 from litesata.phy.k7.trx import K7LiteSATAPHYTRX from litesata.phy.k7.crg import K7LiteSATAPHYCRG - self.trx = K7LiteSATAPHYTRX(pads, speed) - self.crg = K7LiteSATAPHYCRG(pads, self.trx, speed, clk_freq) + self.trx = K7LiteSATAPHYTRX(pads, revision) + self.crg = K7LiteSATAPHYCRG(pads, self.trx, revision, clk_freq) else: msg = "Device" + device + "not (yet) supported." raise NotImplementedError(msg) diff --git a/litesata/phy/k7/crg.py b/litesata/phy/k7/crg.py index 9bfc67eb6..c3267c6c7 100644 --- a/litesata/phy/k7/crg.py +++ b/litesata/phy/k7/crg.py @@ -1,7 +1,7 @@ from litesata.common import * class K7LiteSATAPHYCRG(Module): - def __init__(self, pads, gtx, speed, clk_freq): + def __init__(self, pads, gtx, revision, clk_freq): self.reset = Signal() self.ready = Signal() @@ -34,7 +34,7 @@ class K7LiteSATAPHYCRG(Module): "SATA2" : 8.0, "SATA3" : 4.0 } - mmcm_div = mmcm_div_config[speed] + mmcm_div = mmcm_div_config[revision] self.specials += [ Instance("BUFG", i_I=gtx.txoutclk, o_O=mmcm_clk_i), Instance("MMCME2_ADV", diff --git a/litesata/phy/k7/trx.py b/litesata/phy/k7/trx.py index ad9a9c835..14a3b14e3 100644 --- a/litesata/phy/k7/trx.py +++ b/litesata/phy/k7/trx.py @@ -18,7 +18,7 @@ class _RisingEdge(Module): self.comb += o.eq(i & ~i_d) class K7LiteSATAPHYTRX(Module): - def __init__(self, pads, speed): + def __init__(self, pads, revision): # Common signals # control @@ -105,15 +105,15 @@ class K7LiteSATAPHYTRX(Module): "SATA2" : 2, "SATA3" : 1 } - rxout_div = div_config[speed] - txout_div = div_config[speed] + rxout_div = div_config[revision] + txout_div = div_config[revision] cdr_config = { "SATA1" : 0x0380008BFF40100008, "SATA2" : 0x0388008BFF40200008, "SATA3" : 0X0380008BFF10200010 } - rxcdr_cfg = cdr_config[speed] + rxcdr_cfg = cdr_config[revision] # Specific / Generic signals encoding/decoding self.comb += [ diff --git a/make.py b/make.py index 7f4a1cf8e..28112e489 100644 --- a/make.py +++ b/make.py @@ -8,6 +8,8 @@ from migen.fhdl import simplify from misoclib.gensoc import cpuif +from litesata.common import * + def _import(default, name): return importlib.import_module(default + "." + name) @@ -29,7 +31,7 @@ load-bitstream load bitstream into volatile storage. all clean, build-csr-csv, build-bitstream, load-bitstream. """) - parser.add_argument("-t", "--target", default="bist_kc705", help="Core type to build") + parser.add_argument("-t", "--target", default="bist", help="Core type to build") parser.add_argument("-s", "--sub-target", default="", help="variant of the Core type to build") parser.add_argument("-p", "--platform", default=None, help="platform to build for") parser.add_argument("-Ot", "--target-option", default=[], nargs=2, action="append", help="set target-specific option") @@ -77,21 +79,34 @@ if __name__ == "__main__": print(" "+a) sys.exit(1) - print("""\ -# __ _ __ _______ _________ -# / / (_) /____ / __/ _ /_ __/ _ | -# / /__/ / __/ -_)\ \/ __ |/ / / __ | -# /____/_/\__/\__/___/_/ |_/_/ /_/ |_| -# -# a generic and configurable SATA core -# based on Migen/MiSoC -# -#====== Building options: ====== -# SATA revision: {} -# Integrated BIST: {} -# Integrated Logic Analyzer: {} -# Crossbar ports: {} -#===============================""".format(soc.sata_phy.speed, hasattr(soc.sata, "bist"), hasattr(soc, "mila"), len(soc.sata.crossbar.slaves))) + + revision = soc.sata_phy.revision + frequency = frequencies[soc.sata_phy.revision] + has_bist = hasattr(soc.sata, "bist") + has_crossbar = hasattr(soc.sata, "crossbar") + ports = 1 if not has_crossbar else len(soc.sata.crossbar.slaves) + + print(""" + __ _ __ _______ _________ + / / (_) /____ / __/ _ /_ __/ _ | + / /__/ / __/ -_)\ \/ __ |/ / / __ | + /____/_/\__/\__/___/_/ |_/_/ /_/ |_| + +A small footprint and configurable SATA core + based on Migen/MiSoC + +====== Building options: ====== +SATA revision: {} / {} MHz +BIST: {} +Crossbar: {} +Ports: {} +===============================""".format( + revision, frequency, + has_bist, + has_crossbar, + ports + ) +) # dependencies if actions["all"]: diff --git a/targets/__init__.py b/targets/__init__.py new file mode 100644 index 000000000..e69de29bb diff --git a/targets/bist_kc705.py b/targets/bist.py similarity index 97% rename from targets/bist_kc705.py rename to targets/bist.py index 3818ba8bf..648df127f 100644 --- a/targets/bist_kc705.py +++ b/targets/bist.py @@ -104,12 +104,7 @@ class BISTLeds(Module): sata_rx_cnt = Signal(32) sata_tx_cnt = Signal(32) - sata_freqs_mhz = { - "SATA3" : 150.0, - "SATA2" : 75.0, - "SATA1" : 37.5, - } - sata_freq = int(sata_freqs_mhz[sata_phy.speed]*1000*1000) + sata_freq = int(frequencies[sata_phy.revision]*1000*1000) self.sync.sata_rx += \ If(sata_rx_cnt == 0,