From d892c6f8f57f005822274b331fe76d696e3144e7 Mon Sep 17 00:00:00 2001 From: bunnie Date: Sat, 7 Nov 2020 03:57:46 +0800 Subject: [PATCH] minor bug fixes in spi writing; USB-based flashing is not working --- litex/soc/cores/spi_opi.py | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/litex/soc/cores/spi_opi.py b/litex/soc/cores/spi_opi.py index 4b234f820..0ba76f369 100644 --- a/litex/soc/cores/spi_opi.py +++ b/litex/soc/cores/spi_opi.py @@ -502,7 +502,10 @@ class S7SPIOPI(Module, AutoCSR, AutoDoc): ]) self.wdata = CSRStorage(description="Page data to write to FLASH", fields = [ - CSRField("wdata", size=16, description="16-bit wide write data presented to FLASH, committed to a 128-entry deep FIFO") + CSRField("wdata", size=16, description="""16-bit wide write data presented to FLASH, committed to a 128-entry deep FIFO. + Writes to this register are not cached; note that writes to the SPINOR address space are also committed + to the FIFO, but this space is cached by the CPU, and therefore not guaranteed to be coherent or in order. + The direct wishbone-write address space is provisioned for e.g. USB bus masters that don't have caching.""") ] ) # TODO: implement ECC detailed register readback, CRC checking @@ -918,6 +921,7 @@ class S7SPIOPI(Module, AutoCSR, AutoDoc): ) txphy.act("TX_WRDATA", If(txwr_cnt == 0, + NextValue(txphy_do, self.txwr_fifo.dout), NextState("TX_WR_RESET"), ).Else( NextValue(txwr_cnt, txwr_cnt - 1),