From d89d6dfd0a569eb7868e5735f9f6e7fb1be3c3e6 Mon Sep 17 00:00:00 2001 From: Thomas Watson Date: Sat, 1 Oct 2022 12:28:32 -0500 Subject: [PATCH] soc/cores/clock/intel_common: cleanup --- litex/soc/cores/clock/intel_common.py | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/litex/soc/cores/clock/intel_common.py b/litex/soc/cores/clock/intel_common.py index 513c22cb2..4e5eabd3a 100644 --- a/litex/soc/cores/clock/intel_common.py +++ b/litex/soc/cores/clock/intel_common.py @@ -115,10 +115,10 @@ class IntelClocking(Module, AutoCSR): o_LOCKED = self.locked, ) for n, (clk, f, p, m) in sorted(self.clkouts.items()): - clk_phase_ps = int((1e12/config["clk{}_freq".format(n)])*config["clk{}_phase".format(n)]/360) - self.params["p_CLK{}_DIVIDE_BY".format(n)] = config["clk{}_divide".format(n)] - self.params["p_CLK{}_DUTY_CYCLE".format(n)] = 50 - self.params["p_CLK{}_MULTIPLY_BY".format(n)] = config["m"] - self.params["p_CLK{}_PHASE_SHIFT".format(n)] = clk_phase_ps + clk_phase_ps = int((1e12/config[f"clk{n}_freq"])*config[f"clk{n}_phase"]/360) + self.params[f"p_CLK{n}_DIVIDE_BY"] = config[f"clk{n}_divide"] + self.params[f"p_CLK{n}_DUTY_CYCLE"] = 50 + self.params[f"p_CLK{n}_MULTIPLY_BY"] = config["m"] + self.params[f"p_CLK{n}_PHASE_SHIFT"] = clk_phase_ps self.comb += clk.eq(clks[n]) self.specials += Instance("ALTPLL", **self.params)