From d8ac9362066eb88d0aef8cf883915f910a2eca7a Mon Sep 17 00:00:00 2001 From: Tim 'mithro' Ansell Date: Fri, 21 Jun 2019 12:03:30 -0700 Subject: [PATCH] Convert top level comment to a docstring. --- litex/soc/cores/up5kspram.py | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/litex/soc/cores/up5kspram.py b/litex/soc/cores/up5kspram.py index 573f86405..a4d79f25d 100644 --- a/litex/soc/cores/up5kspram.py +++ b/litex/soc/cores/up5kspram.py @@ -1,11 +1,13 @@ from migen import * from litex.soc.interconnect import wishbone -# ICE40 UltraPlus family-specific Wishbone interface to the Single Port RAM -# (SPRAM) primitives. Because SPRAM is much more coarse grained than Block -# RAM resources, this RAM is only minimally configurable at present (64kB or -# 128kB). Because it is single port, this module is meant to be used as the -# CPU's RAM region, leaving block RAM free for other use. +""" +ICE40 UltraPlus family-specific Wishbone interface to the Single Port RAM +(SPRAM) primitives. Because SPRAM is much more coarse grained than Block +RAM resources, this RAM is only minimally configurable at present (64kB or +128kB). Because it is single port, this module is meant to be used as the +CPU's RAM region, leaving block RAM free for other use. +""" class Up5kSPRAM(Module): def __init__(self, width=32, size=64*1024):