From d9b15e6ef64691dc6cf4de5c4fe3d62ed4bf1b33 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 12 May 2015 15:49:20 +0200 Subject: [PATCH] cores: replace Timeout with new WaitTimer --- misoclib/com/liteeth/common.py | 2 +- misoclib/com/liteeth/core/arp/__init__.py | 18 +++++----- misoclib/com/liteusb/core/packet.py | 15 ++++---- misoclib/mem/litesata/common.py | 2 +- misoclib/mem/litesata/phy/ctrl.py | 22 ++++++------ misoclib/mem/litesata/phy/k7/crg.py | 43 ++++++++++------------- misoclib/mem/litesata/phy/k7/trx.py | 9 ++--- misoclib/tools/litescope/common.py | 2 +- misoclib/tools/wishbone.py | 12 +++---- 9 files changed, 54 insertions(+), 71 deletions(-) diff --git a/misoclib/com/liteeth/common.py b/misoclib/com/liteeth/common.py index f933a34ed..e70ad8585 100644 --- a/misoclib/com/liteeth/common.py +++ b/misoclib/com/liteeth/common.py @@ -5,7 +5,7 @@ from migen.fhdl.std import * from migen.genlib.resetsync import AsyncResetSynchronizer from migen.genlib.record import * from migen.genlib.fsm import FSM, NextState -from migen.genlib.misc import chooser, reverse_bytes, FlipFlop, Counter, Timeout +from migen.genlib.misc import chooser, reverse_bytes, FlipFlop, Counter, WaitTimer from migen.flow.actor import * from migen.actorlib.structuring import Converter, Pipeline from migen.actorlib.fifo import SyncFIFO, AsyncFIFO diff --git a/misoclib/com/liteeth/core/arp/__init__.py b/misoclib/com/liteeth/core/arp/__init__.py index b46522a5a..a78a30cc1 100644 --- a/misoclib/com/liteeth/core/arp/__init__.py +++ b/misoclib/com/liteeth/core/arp/__init__.py @@ -146,13 +146,13 @@ class LiteEthARPTable(Module): # # # - request_timeout = Timeout(clk_freq//10) + request_timer = WaitTimer(clk_freq//10) request_counter = Counter(max=max_requests) request_pending = FlipFlop() request_ip_address = FlipFlop(32) - self.submodules += request_timeout, request_counter, request_pending, request_ip_address + self.submodules += request_timer, request_counter, request_pending, request_ip_address self.comb += [ - request_timeout.ce.eq(request_pending.q), + request_timer.wait.eq(request_pending.q & ~request_counter.ce), request_pending.d.eq(1), request_ip_address.d.eq(request.ip_address) ] @@ -164,8 +164,8 @@ class LiteEthARPTable(Module): cached_valid = Signal() cached_ip_address = Signal(32) cached_mac_address = Signal(48) - cached_timeout = Timeout(clk_freq*10) - self.submodules += cached_timeout + cached_timer = WaitTimer(clk_freq*10) + self.submodules += cached_timer self.submodules.fsm = fsm = FSM(reset_state="IDLE") fsm.act("IDLE", @@ -177,7 +177,7 @@ class LiteEthARPTable(Module): NextState("UPDATE_TABLE"), ).Elif(request_counter.value == max_requests-1, NextState("PRESENT_RESPONSE") - ).Elif(request.stb | (request_pending.q & request_timeout.reached), + ).Elif(request.stb | (request_pending.q & request_timer.done), NextState("CHECK_TABLE") ) ) @@ -199,10 +199,9 @@ class LiteEthARPTable(Module): cached_valid.eq(1), cached_ip_address.eq(sink.ip_address), cached_mac_address.eq(sink.mac_address), - cached_timeout.reset.eq(1) ).Else( - cached_timeout.ce.eq(1), - If(cached_timeout.reached, + cached_timer.wait.eq(1), + If(cached_timer.done, cached_valid.eq(0) ) ) @@ -230,7 +229,6 @@ class LiteEthARPTable(Module): source.request.eq(1), source.ip_address.eq(request_ip_address.q), If(source.ack, - request_timeout.reset.eq(1), request_counter.reset.eq(request.stb), request_counter.ce.eq(1), request_pending.ce.eq(1), diff --git a/misoclib/com/liteusb/core/packet.py b/misoclib/com/liteusb/core/packet.py index 43c97b014..f256e7d17 100644 --- a/misoclib/com/liteusb/core/packet.py +++ b/misoclib/com/liteusb/core/packet.py @@ -1,6 +1,6 @@ from misoclib.com.liteusb.common import * from migen.actorlib.structuring import Pack, Unpack -from migen.genlib.misc import Timeout +from migen.genlib.misc import WaitTimer class LiteUSBPacketizer(Module): def __init__(self): @@ -116,16 +116,13 @@ class LiteUSBDepacketizer(Module): header_pack.source.ack.eq(1), ) - self.submodules.timeout = Timeout(clk_freq*timeout) - self.comb += [ - self.timeout.reset.eq(fsm.ongoing("IDLE")), - self.timeout.ce.eq(1) - ] + self.submodules.timer = WaitTimer(clk_freq*timeout) + self.comb += self.timer.wait.eq(~fsm.ongoing("IDLE")) fsm.act("RECEIVE_HEADER", header_pack.sink.stb.eq(sink.stb), header_pack.sink.payload.eq(sink.payload), - If(self.timeout.reached, + If(self.timer.done, NextState("IDLE") ).Elif(header_pack.source.stb, NextState("COPY") @@ -134,7 +131,7 @@ class LiteUSBDepacketizer(Module): ) ) - self.comb += header_pack.reset.eq(self.timeout.reached) + self.comb += header_pack.reset.eq(self.timer.done) sop = Signal() eop = Signal() @@ -146,7 +143,7 @@ class LiteUSBDepacketizer(Module): source.eop.eq(eop), source.data.eq(sink.data), sink.ack.eq(source.ack), - If((source.stb & source.ack & eop) | self.timeout.reached, + If((source.stb & source.ack & eop) | self.timer.done NextState("IDLE") ) ) diff --git a/misoclib/mem/litesata/common.py b/misoclib/mem/litesata/common.py index 44a0ee19f..c7fb6e281 100644 --- a/misoclib/mem/litesata/common.py +++ b/misoclib/mem/litesata/common.py @@ -5,7 +5,7 @@ from migen.fhdl.decorators import ModuleTransformer from migen.genlib.resetsync import * from migen.genlib.fsm import * from migen.genlib.record import * -from migen.genlib.misc import chooser, optree, Counter, Timeout +from migen.genlib.misc import chooser, optree, Counter, WaitTimer from migen.genlib.cdc import * from migen.flow.actor import * from migen.flow.plumbing import Multiplexer, Demultiplexer diff --git a/misoclib/mem/litesata/phy/ctrl.py b/misoclib/mem/litesata/phy/ctrl.py index 3c53c6b38..755f5271b 100644 --- a/misoclib/mem/litesata/phy/ctrl.py +++ b/misoclib/mem/litesata/phy/ctrl.py @@ -15,9 +15,9 @@ class LiteSATAPHYCtrl(Module): sink.ack.eq(1) ] - retry_timeout = Timeout(self.us(10000)) - align_timeout = Timeout(self.us(873)) - self.submodules += align_timeout, retry_timeout + retry_timer = WaitTimer(self.us(10000)) + align_timer = WaitTimer(self.us(873)) + self.submodules += align_timer, retry_timer align_detect = Signal() non_align_cnt = Signal(4) @@ -26,11 +26,9 @@ class LiteSATAPHYCtrl(Module): self.fsm = fsm = InsertReset(FSM(reset_state="RESET")) self.submodules += fsm - self.comb += fsm.reset.eq(retry_timeout.reached | align_timeout.reached) + self.comb += fsm.reset.eq(retry_timer.done | align_timer.done) fsm.act("RESET", trx.tx_idle.eq(1), - retry_timeout.reset.eq(1), - align_timeout.reset.eq(1), non_align_counter.reset.eq(1), If(crg.ready, NextState("COMINIT") @@ -45,14 +43,14 @@ class LiteSATAPHYCtrl(Module): ) fsm.act("AWAIT_COMINIT", trx.tx_idle.eq(1), - retry_timeout.ce.eq(1), + retry_timer.wait.eq(1), If(trx.rx_cominit_stb, NextState("AWAIT_NO_COMINIT") ) ) fsm.act("AWAIT_NO_COMINIT", trx.tx_idle.eq(1), - retry_timeout.reset.eq(1), + retry_timer.wait.eq(1), If(~trx.rx_cominit_stb, NextState("CALIBRATE") ) @@ -70,7 +68,7 @@ class LiteSATAPHYCtrl(Module): ) fsm.act("AWAIT_COMWAKE", trx.tx_idle.eq(1), - retry_timeout.ce.eq(1), + retry_timer.wait.eq(1), If(trx.rx_comwake_stb, NextState("AWAIT_NO_COMWAKE") ) @@ -85,7 +83,7 @@ class LiteSATAPHYCtrl(Module): trx.tx_idle.eq(0), source.data.eq(0x4A4A4A4A), # D10.2 source.charisk.eq(0b0000), - align_timeout.ce.eq(1), + align_timer.wait.eq(1), If(~trx.rx_idle, NextState("AWAIT_ALIGN"), crg.tx_reset.eq(1), @@ -97,7 +95,7 @@ class LiteSATAPHYCtrl(Module): source.data.eq(0x4A4A4A4A), # D10.2 source.charisk.eq(0b0000), trx.rx_align.eq(1), - align_timeout.ce.eq(1), + align_timer.wait.eq(1), If(align_detect & ~trx.rx_idle, NextState("SEND_ALIGN") ) @@ -105,7 +103,7 @@ class LiteSATAPHYCtrl(Module): fsm.act("SEND_ALIGN", trx.tx_idle.eq(0), trx.rx_align.eq(1), - align_timeout.ce.eq(1), + align_timer.wait.eq(1), source.data.eq(primitives["ALIGN"]), source.charisk.eq(0b0001), If(sink.stb, diff --git a/misoclib/mem/litesata/phy/k7/crg.py b/misoclib/mem/litesata/phy/k7/crg.py index 73a7d9668..bd853af5b 100644 --- a/misoclib/mem/litesata/phy/k7/crg.py +++ b/misoclib/mem/litesata/phy/k7/crg.py @@ -78,12 +78,9 @@ class K7LiteSATAPHYCRG(Module): # After configuration, GTX's resets have to stay low for at least 500ns # See AR43482 startup_cycles = math.ceil(500*clk_freq/1000000000) - startup_wait = Timeout(startup_cycles) - self.submodules += startup_wait - self.comb += [ - startup_wait.reset.eq(self.tx_reset | self.rx_reset), - startup_wait.ce.eq(1) - ] + startup_timer = WaitTimer(startup_cycles) + self.submodules += startup_timer + self.comb += startup_timer.wait.eq(~(self.tx_reset | self.rx_reset)) # TX Startup FSM self.tx_ready = Signal() @@ -91,7 +88,7 @@ class K7LiteSATAPHYCRG(Module): self.submodules += tx_startup_fsm # Wait 500ns of AR43482 tx_startup_fsm.act("IDLE", - If(startup_wait.reached, + If(startup_timer.done, NextState("RESET_ALL"), ) ) @@ -144,12 +141,11 @@ class K7LiteSATAPHYCRG(Module): self.tx_ready.eq(1) ) - tx_ready_timeout = Timeout(1*clk_freq//1000) - self.submodules += tx_ready_timeout + tx_ready_timer = WaitTimer(1*clk_freq//1000) + self.submodules += tx_ready_timer self.comb += [ - tx_ready_timeout.reset.eq(self.tx_reset | self.tx_ready), - tx_ready_timeout.ce.eq(~self.tx_ready), - tx_startup_fsm.reset.eq(self.tx_reset | tx_ready_timeout.reached), + tx_ready_timer.wait.eq(~self.tx_ready), + tx_startup_fsm.reset.eq(self.tx_reset | tx_ready_timer.done), ] @@ -158,14 +154,12 @@ class K7LiteSATAPHYCRG(Module): rx_startup_fsm = InsertReset(FSM(reset_state="IDLE")) self.submodules += rx_startup_fsm - cdr_stable = Timeout(2048) - self.submodules += cdr_stable - self.comb += cdr_stable.ce.eq(1), + cdr_stable_timer = WaitTimer(2048) + self.submodules += cdr_stable_timer # Wait 500ns of AR43482 rx_startup_fsm.act("IDLE", - cdr_stable.reset.eq(1), - If(startup_wait.reached, + If(startup_timer.done, NextState("RESET_GTX"), ) ) @@ -178,8 +172,7 @@ class K7LiteSATAPHYCRG(Module): rx_startup_fsm.act("WAIT_CPLL", gtx.gtrxreset.eq(1), If(gtx.cplllock, - NextState("RELEASE_GTX"), - cdr_stable.reset.eq(1) + NextState("RELEASE_GTX") ) ) # Release GTX reset and wait for GTX resetdone @@ -187,7 +180,8 @@ class K7LiteSATAPHYCRG(Module): # of gttxreset) rx_startup_fsm.act("RELEASE_GTX", gtx.rxuserrdy.eq(1), - If(gtx.rxresetdone & cdr_stable.reached, + cdr_stable_timer.wait.eq(1), + If(gtx.rxresetdone & cdr_stable_timer.done, NextState("ALIGN") ) ) @@ -209,12 +203,11 @@ class K7LiteSATAPHYCRG(Module): self.rx_ready.eq(1) ) - rx_ready_timeout = Timeout(1*clk_freq//1000) - self.submodules += rx_ready_timeout + rx_ready_timer = WaitTimer(1*clk_freq//1000) + self.submodules += rx_ready_timer self.comb += [ - rx_ready_timeout.reset.eq(self.rx_reset | self.rx_ready), - rx_ready_timeout.ce.eq(~self.rx_ready), - rx_startup_fsm.reset.eq(self.rx_reset | rx_ready_timeout.reached), + rx_ready_timer.wait.eq(~self.rx_ready), + rx_startup_fsm.reset.eq(self.rx_reset | rx_ready_timer.done), ] # Ready diff --git a/misoclib/mem/litesata/phy/k7/trx.py b/misoclib/mem/litesata/phy/k7/trx.py index 628e4506b..d3a34ca01 100644 --- a/misoclib/mem/litesata/phy/k7/trx.py +++ b/misoclib/mem/litesata/phy/k7/trx.py @@ -24,17 +24,14 @@ class _RisingEdge(Module): class _LowPassFilter(Module): def __init__(self, i, o, cycles): i_d = Signal() - self.submodules.timeout = Timeout(cycles) + self.submodules.timer = WaitTimer(cycles) self.sync += [ i_d.eq(i), - If(self.timeout.reached, + If(self.timer.done, o.eq(i_d) ) ] - self.comb += [ - self.timeout.reset.eq(i != i_d), - self.timeout.ce.eq(1) - ] + self.comb += self.timer.wait.eq(i == i_d) class K7LiteSATAPHYTRX(Module): diff --git a/misoclib/tools/litescope/common.py b/misoclib/tools/litescope/common.py index 51a4ca95f..4b51c092b 100644 --- a/misoclib/tools/litescope/common.py +++ b/misoclib/tools/litescope/common.py @@ -2,7 +2,7 @@ from migen.fhdl.std import * from migen.bank.description import * from migen.genlib.fsm import FSM, NextState from migen.flow.actor import * -from migen.genlib.misc import Counter, Timeout +from migen.genlib.misc import Counter from migen.actorlib.fifo import AsyncFIFO, SyncFIFO from migen.flow.plumbing import Buffer from migen.fhdl.specials import Memory diff --git a/misoclib/tools/wishbone.py b/misoclib/tools/wishbone.py index 50ab287fc..5b712bf8f 100644 --- a/misoclib/tools/wishbone.py +++ b/misoclib/tools/wishbone.py @@ -1,6 +1,6 @@ from migen.fhdl.std import * from migen.bus import wishbone -from migen.genlib.misc import chooser, Counter, Timeout +from migen.genlib.misc import chooser, Counter, WaitTimer from migen.genlib.record import Record from migen.genlib.fsm import FSM, NextState from migen.flow.actor import Sink, Source @@ -46,15 +46,13 @@ class WishboneStreamingBridge(Module): ] fsm = InsertReset(FSM(reset_state="IDLE")) - timeout = Timeout(clk_freq//10) - self.submodules += fsm, timeout + timer = WaitTimer(clk_freq//10) + self.submodules += fsm, timer self.comb += [ - timeout.ce.eq(1), - fsm.reset.eq(timeout.reached), + fsm.reset.eq(timer.done), phy.source.ack.eq(1) ] fsm.act("IDLE", - timeout.reset.eq(1), If(phy.source.stb, cmd_ce.eq(1), If((phy.source.data == self.cmds["write"]) | @@ -140,6 +138,8 @@ class WishboneStreamingBridge(Module): ) ) + self.comb += timer.wait.eq(~fsm.ongoing("IDLE")) + if phy.sink.description.packetized: self.comb += [ phy.sink.sop.eq((byte_counter.value == 0) & (word_counter.value == 0)),