From d9b6d7608c903c89ec4e69998519ffbc16875c68 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 12 Mar 2021 09:03:17 +0100 Subject: [PATCH] soc/integration/soc_core: Cleanup SoCCore arguments. --- litex/soc/integration/soc_core.py | 96 +++++++++++++------------------ 1 file changed, 39 insertions(+), 57 deletions(-) diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py index c6b4cf920..596835597 100644 --- a/litex/soc/integration/soc_core.py +++ b/litex/soc/integration/soc_core.py @@ -256,67 +256,49 @@ class SoCCore(LiteXSoC): def soc_core_args(parser): # Bus parameters - parser.add_argument("--bus-standard", default="wishbone", - help="select bus standard: {}, (default=wishbone)".format( - ", ".join(SoCBusHandler.supported_standard))) - parser.add_argument("--bus-data-width", default=32, type=auto_int, - help="Bus data width (default=32)") - parser.add_argument("--bus-address-width", default=32, type=auto_int, - help="Bus address width (default=32)") - parser.add_argument("--bus-timeout", default=1e6, type=float, - help="Bus timeout in cycles (default=1e6)") + parser.add_argument("--bus-standard", default="wishbone", help="Select bus standard: {}, (default=wishbone).".format(", ".join(SoCBusHandler.supported_standard))) + parser.add_argument("--bus-data-width", default=32, type=auto_int, help="Bus data-width (default=32).") + parser.add_argument("--bus-address-width", default=32, type=auto_int, help="Bus address-width (default=32).") + parser.add_argument("--bus-timeout", default=1e6, type=float, help="Bus timeout in cycles (default=1e6).") # CPU parameters - parser.add_argument("--cpu-type", default=None, - help="select CPU: {}, (default=vexriscv)".format(", ".join(iter(cpu.CPUS.keys())))) - parser.add_argument("--cpu-variant", default=None, - help="select CPU variant, (default=standard)") - parser.add_argument("--cpu-reset-address", default=None, type=auto_int, - help="CPU reset address (default=None (Integrated ROM)") - # ROM parameters - parser.add_argument("--integrated-rom-size", default=0x8000, type=auto_int, - help="size/enable the integrated (BIOS) ROM (default=32KB)") - parser.add_argument("--integrated-rom-file", default=None, type=str, - help="integrated (BIOS) ROM binary file") - # SRAM parameters - parser.add_argument("--integrated-sram-size", default=0x2000, type=auto_int, - help="size/enable the integrated SRAM (default=8KB)") - # MAIN_RAM parameters - parser.add_argument("--integrated-main-ram-size", default=None, type=auto_int, - help="size/enable the integrated main RAM") - # CSR parameters - parser.add_argument("--csr-data-width", default=None, type=auto_int, - help="CSR bus data-width (8 or 32, default=32)") - parser.add_argument("--csr-address-width", default=14, type=auto_int, - help="CSR bus address-width") - parser.add_argument("--csr-paging", default=0x800, type=auto_int, - help="CSR bus paging") - parser.add_argument("--csr-ordering", default="big", - help="CSR registers ordering (default=big)") - - # Identifier parameters - parser.add_argument("--ident", default=None, type=str, - help="SoC identifier (default=\"\"") - parser.add_argument("--ident-version", default=None, type=bool, - help="add date/time to SoC identifier (default=False)") - # UART parameters - parser.add_argument("--no-uart", action="store_true", - help="Disable UART (default=False)") - parser.add_argument("--uart-name", default="serial", type=str, - help="UART type/name (default=serial)") - parser.add_argument("--uart-baudrate", default=None, type=auto_int, - help="UART baudrate (default=115200)") - parser.add_argument("--uart-fifo-depth", default=16, type=auto_int, - help="UART FIFO depth (default=16)") - # Timer parameters - parser.add_argument("--no-timer", action="store_true", - help="Disable Timer (default=False)") - parser.add_argument("--timer-uptime", action="store_true", - help="Add an uptime register to the timer (default=False)") + parser.add_argument("--cpu-type", default=None, help="Select CPU: {}, (default=vexriscv).".format(", ".join(iter(cpu.CPUS.keys())))) + parser.add_argument("--cpu-variant", default=None, help="CPU variant (default=standard).") + parser.add_argument("--cpu-reset-address", default=None, type=auto_int, help="CPU reset address (default=None : Boot from Integrated ROM).") # Controller parameters - parser.add_argument("--no-ctrl", action="store_true", - help="Disable Controller (default=False)") + parser.add_argument("--no-ctrl", action="store_true", help="Disable Controller (default=False).") + + # ROM parameters + parser.add_argument("--integrated-rom-size", default=0x8000, type=auto_int, help="Size/Enable the integrated (BIOS) ROM (default=32KB).") + parser.add_argument("--integrated-rom-file", default=None, type=str, help="Integrated (BIOS) ROM binary file.") + + # SRAM parameters + parser.add_argument("--integrated-sram-size", default=0x2000, type=auto_int, help="Size/Enable the integrated SRAM (default=8KB).") + + # MAIN_RAM parameters + parser.add_argument("--integrated-main-ram-size", default=None, type=auto_int, help="size/enable the integrated main RAM") + + # CSR parameters + parser.add_argument("--csr-data-width", default=None, type=auto_int, help="CSR bus data-width (8 or 32, default=32).") + parser.add_argument("--csr-address-width", default=14, type=auto_int, help="CSR bus address-width.") + parser.add_argument("--csr-paging", default=0x800, type=auto_int, help="CSR bus paging.") + parser.add_argument("--csr-ordering", default="big", help="CSR registers ordering (default=big).") + + # Identifier parameters + parser.add_argument("--ident", default=None, type=str, help="SoC identifier (default=\"\").") + parser.add_argument("--ident-version", default=None, type=bool, help="Add date/time to SoC identifier (default=False)") + + # UART parameters + parser.add_argument("--no-uart", action="store_true", help="Disable UART (default=False).") + parser.add_argument("--uart-name", default="serial", type=str, help="UART type/name (default=serial).") + parser.add_argument("--uart-baudrate", default=None, type=auto_int, help="UART baudrate (default=115200).") + parser.add_argument("--uart-fifo-depth", default=16, type=auto_int, help="UART FIFO depth (default=16).") + + # Timer parameters + parser.add_argument("--no-timer", action="store_true", help="Disable Timer (default=False).") + parser.add_argument("--timer-uptime", action="store_true", help="Add an uptime capability to Timer (default=False).") + def soc_core_argdict(args): r = dict()