diff --git a/litex/build/generic_platform.py b/litex/build/generic_platform.py
index b40a3ad7a..4b4511cd7 100644
--- a/litex/build/generic_platform.py
+++ b/litex/build/generic_platform.py
@@ -18,11 +18,14 @@ from litex.gen.fhdl import verilog
 from litex.build.io import CRG
 from litex.build import tools
 
+# --------------------------------------------------------------------------------------------------
 
 class ConstraintError(Exception):
     pass
 
 
+# IOS ----------------------------------------------------------------------------------------------
+
 class Pins:
     def __init__(self, *identifiers):
         self.identifiers = []
@@ -33,8 +36,7 @@ class Pins:
                 self.identifiers += i.split()
 
     def __repr__(self):
-        return "{}('{}')".format(self.__class__.__name__,
-                                 " ".join(self.identifiers))
+        return "{}('{}')".format(self.__class__.__name__, " ".join(self.identifiers))
 
 
 class IOStandard:
@@ -69,15 +71,15 @@ class Inverted:
 
 class Subsignal:
     def __init__(self, name, *constraints):
-        self.name = name
+        self.name        = name
         self.constraints = list(constraints)
 
     def __repr__(self):
-        return "{}('{}', {})".format(
-            self.__class__.__name__,
+        return "{}('{}', {})".format(self.__class__.__name__,
             self.name,
             ", ".join([repr(constr) for constr in self.constraints]))
 
+# Platform -----------------------------------------------------------------------------------------
 
 class PlatformInfo:
     def __init__(self, info):
@@ -111,7 +113,7 @@ def _resource_type(resource):
                 i = []
 
             assert(isinstance(t, list))
-            n_bits = None
+            n_bits   = None
             inverted = False
             for c in element.constraints:
                 if isinstance(c, Pins):
@@ -125,12 +127,13 @@ def _resource_type(resource):
 
     return t, i
 
+# Connector Manager --------------------------------------------------------------------------------
 
 class ConnectorManager:
     def __init__(self, connectors):
         self.connector_table = dict()
         for connector in connectors:
-            cit = iter(connector)
+            cit       = iter(connector)
             conn_name = next(cit)
             if isinstance(connector[1], str):
                 pin_list = []
@@ -164,7 +167,7 @@ class ConnectorManager:
 
 
 def _separate_pins(constraints):
-    pins = None
+    pins   = None
     others = []
     for c in constraints:
         if isinstance(c, Pins):
@@ -175,11 +178,12 @@ def _separate_pins(constraints):
 
     return pins, others
 
+# Constraint Manager -------------------------------------------------------------------------------
 
 class ConstraintManager:
     def __init__(self, io, connectors):
-        self.available = list(io)
-        self.matched = []
+        self.available         = list(io)
+        self.matched           = []
         self.platform_commands = []
         self.connector_manager = ConnectorManager(connectors)
 
@@ -258,9 +262,9 @@ class ConstraintManager:
     def get_sig_constraints(self):
         r = []
         for resource, obj in self.matched:
-            name = resource[0]
-            number = resource[1]
-            has_subsignals = False
+            name            = resource[0]
+            number          = resource[1]
+            has_subsignals  = False
             top_constraints = []
             for element in resource[2:]:
                 if isinstance(element, Subsignal):
@@ -287,10 +291,11 @@ class ConstraintManager:
     def get_platform_commands(self):
         return self.platform_commands
 
+# Generic Platform ---------------------------------------------------------------------------------
 
 class GenericPlatform:
     def __init__(self, device, io, connectors=[], name=None):
-        self.device = device
+        self.device             = device
         self.constraint_manager = ConstraintManager(io, connectors)
         if name is None:
             # Get name from Platform file.
@@ -298,12 +303,12 @@ class GenericPlatform:
         if name == "__main__":
             # If no Platform file, use script filename,
             name = os.path.splitext(os.path.basename(sys.argv[0]))[0]
-        self.name = name
-        self.sources = []
+        self.name                  = name
+        self.sources               = []
         self.verilog_include_paths = []
-        self.output_dir = None
-        self.finalized = False
-        self.use_default_clk = False
+        self.output_dir            = None
+        self.finalized             = False
+        self.use_default_clk       = False
 
     def request(self, *args, **kwargs):
         return self.constraint_manager.request(*args, **kwargs)
@@ -335,7 +340,7 @@ class GenericPlatform:
     def finalize(self, fragment, *args, **kwargs):
         if self.finalized:
             raise ConstraintError("Already finalized")
-        # if none exists, create a default clock domain and drive it
+        # If none exists, create a default clock domain and drive it.
         if not fragment.clock_domains:
             if not hasattr(self, "default_clk_name"):
                 raise NotImplementedError(
@@ -348,8 +353,7 @@ class GenericPlatform:
         self.finalized = True
 
     def do_finalize(self, fragment, *args, **kwargs):
-        """overload this and e.g. add_platform_command()'s after the modules
-        had their say"""
+        # Overload this and e.g. add_platform_command()'s after the modules had their say.
         if self.use_default_clk and hasattr(self, "default_clk_period"):
             try:
                 self.add_period_constraint(
@@ -393,11 +397,11 @@ class GenericPlatform:
         self.verilog_include_paths.append(os.path.abspath(path))
 
     def resolve_signals(self, vns):
-        # resolve signal names in constraints
+        # Resolve signal names in constraints.
         sc = self.constraint_manager.get_sig_constraints()
         named_sc = [(vns.get_name(sig), pins, others, resource)
                     for sig, pins, others, resource in sc]
-        # resolve signal names in platform commands
+        # Resolve signal names in platform commands.
         pc = self.constraint_manager.get_platform_commands()
         named_pc = []
         for template, args in pc: