From da3a178bc62a3463ee001eb9acca3252200c99b9 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 16 Dec 2019 11:13:10 +0100 Subject: [PATCH] soc/cores/pwm: add clock_domain support --- litex/soc/cores/pwm.py | 19 +++++++++++-------- 1 file changed, 11 insertions(+), 8 deletions(-) diff --git a/litex/soc/cores/pwm.py b/litex/soc/cores/pwm.py index 8a5ff08bc..6b28c393d 100644 --- a/litex/soc/cores/pwm.py +++ b/litex/soc/cores/pwm.py @@ -16,7 +16,7 @@ class PWM(Module, AutoCSR): Pulse Width Modulation can be useful for various purposes: dim leds, regulate a fan, control an oscillator. Software can configure the PWM width and period and enable/disable it. """ - def __init__(self, pwm=None, with_csr=True): + def __init__(self, pwm=None, clock_domain="sys", with_csr=True): if pwm is None: self.pwm = pwm = Signal() self.enable = Signal() @@ -27,7 +27,8 @@ class PWM(Module, AutoCSR): counter = Signal(32) - self.sync += [ + sync = getattr(self.sync, clock_domain) + sync += [ If(self.enable, counter.eq(counter + 1), If(counter < self.width, @@ -45,15 +46,17 @@ class PWM(Module, AutoCSR): ] if with_csr: - self.add_csr() + self.add_csr(clock_domain) - def add_csr(self): + def add_csr(self, clock_domain): self._enable = CSRStorage() self._width = CSRStorage(32) self._period = CSRStorage(32) - self.comb += [ - self.enable.eq(self._enable.storage), - self.width.eq(self._width.storage), - self.period.eq(self._period.storage) + n = 0 if clock_domain == "sys" else 2 + print(n) + self.specials += [ + MultiReg(self._enable.storage, self.enable, n=n), + MultiReg(self._width.storage, self.width, n=n), + MultiReg(self._period.storage, self.period, n=n), ]