From da91aa43f7486d5404db3e1dbcd947f9e3de0f52 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Sat, 28 Sep 2019 14:13:39 +0200 Subject: [PATCH] soc_core/cpu: move memory map override to CPUs, select reset_address after eventual memory map has override been done --- litex/soc/cores/cpu/mor1kx/core.py | 15 +++++++++++ litex/soc/cores/cpu/rocket/core.py | 11 +++++++- litex/soc/integration/soc_core.py | 42 +++++++++++------------------- 3 files changed, 40 insertions(+), 28 deletions(-) diff --git a/litex/soc/cores/cpu/mor1kx/core.py b/litex/soc/cores/cpu/mor1kx/core.py index 5532a0435..46f55e651 100644 --- a/litex/soc/cores/cpu/mor1kx/core.py +++ b/litex/soc/cores/cpu/mor1kx/core.py @@ -24,6 +24,18 @@ class MOR1KX(Module): def endianness(self): return "big" + @property + def mem_map_linux(self): + # Mainline Linux OpenRISC arch code requires Linux kernel to be loaded at the physical + # address of 0x0. As we are running Linux from the MAIN_RAM region - move it to satisfy + # that requirement. + return { + "main_ram" : 0x00000000, + "rom" : 0x10000000, + "sram" : 0x50000000, + "csr" : 0x60000000, + } + @property def gcc_triple(self): return "or1k-elf" @@ -67,6 +79,9 @@ class MOR1KX(Module): self.dbus = d = wishbone.Interface() self.interrupt = Signal(32) + if variant == "linux": + self.mem_map = self.mem_map_linux + # # # cpu_args = dict( diff --git a/litex/soc/cores/cpu/rocket/core.py b/litex/soc/cores/cpu/rocket/core.py index a9334aa38..a048c3ce8 100644 --- a/litex/soc/cores/cpu/rocket/core.py +++ b/litex/soc/cores/cpu/rocket/core.py @@ -57,6 +57,15 @@ class RocketRV64(Module): def endianness(self): return "little" + @property + def mem_map(self): + # Rocket reserves the first 256Mbytes for internal use, so we must change default mem_map. + return { + "rom" : 0x10000000, + "sram" : 0x11000000, + "csr" : 0x12000000, + } + @property def gcc_triple(self): return ("riscv64-unknown-elf") @@ -100,7 +109,7 @@ class RocketRV64(Module): # # # - self.cpu_params += dict( + self.cpu_params = dict( # clock, reset i_clock=ClockSignal(), i_reset=ResetSignal() | self.reset, diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py index f0ec4c975..51a319dea 100644 --- a/litex/soc/integration/soc_core.py +++ b/litex/soc/integration/soc_core.py @@ -192,39 +192,19 @@ class SoCCore(Module): self._csr_masters = [] # Parameters managment --------------------------------------------------------------------- - - # NOTE: RocketChip reserves the first 256Mbytes for internal use, - # so we must change default mem_map; - # Also, CSRs *must* be 64-bit aligned. - if cpu_type == "rocket": - self.soc_mem_map["rom"] = 0x10000000 - self.soc_mem_map["sram"] = 0x11000000 - self.soc_mem_map["csr"] = 0x12000000 - csr_alignment = 64 - - # Mainline Linux OpenRISC arch code requires Linux kernel to be loaded - # at the physical address of 0x0. As we are running Linux from the - # MAIN_RAM region - move it to satisfy that requirement. - if cpu_type == "mor1kx" and cpu_variant == "linux": - self.soc_mem_map["main_ram"] = 0x00000000 - self.soc_mem_map["rom"] = 0x10000000 - self.soc_mem_map["sram"] = 0x50000000 - self.soc_mem_map["csr"] = 0x60000000 - if cpu_type == "None": cpu_type = None + # FIXME: On RocketChip, CSRs *must* be 64-bit aligned. + if cpu_type == "rocket": + csr_alignment = 64 + if not with_wishbone: self.soc_mem_map["csr"] = 0x00000000 self.cpu_type = cpu_type self.cpu_variant = cpu.check_format_cpu_variant(cpu_variant) - if integrated_rom_size: - cpu_reset_address = self.soc_mem_map["rom"] - self.cpu_reset_address = cpu_reset_address - self.config["CPU_RESET_ADDR"] = self.cpu_reset_address - self.shadow_base = shadow_base self.integrated_rom_size = integrated_rom_size @@ -263,11 +243,19 @@ class SoCCore(Module): if cpu_type is not None: if cpu_variant is not None: self.config["CPU_VARIANT"] = str(cpu_variant.split('+')[0]).upper() - # CPU selection / instance + # Check type if cpu_type not in cpu.CPUS.keys(): raise ValueError("Unsupported CPU type: {}".format(cpu_type)) + # Add the CPU self.add_cpu(cpu.CPUS[cpu_type](platform, self.cpu_variant)) - self.cpu.set_reset_address(cpu_reset_address) + + # Override Memory Map (if needed by CPU) + if hasattr(self.cpu, "mem_map"): + self.soc_mem_map.update(self.cpu.mem_map) + + # Set reset address + self.cpu.set_reset_address(self.soc_mem_map["rom"] if integrated_rom_size else cpu_reset_address) + self.config["CPU_RESET_ADDR"] = self.cpu.reset_address # Add Instruction/Data buses as Wisbone masters self.add_wb_master(self.cpu.ibus) @@ -455,7 +443,7 @@ class SoCCore(Module): def register_rom(self, interface, rom_size=0xa000): self.add_wb_slave(self.soc_mem_map["rom"], interface, rom_size) - self.add_memory_region("rom", self.cpu_reset_address, rom_size) + self.add_memory_region("rom", self.cpu.reset_address, rom_size) def get_memory_regions(self): return self._memory_regions