diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py
index 0909d55df..fcef80687 100644
--- a/litex/soc/integration/soc.py
+++ b/litex/soc/integration/soc.py
@@ -1359,7 +1359,7 @@ class LiteXSoC(SoC):
                 base_address = self.bus.regions["main_ram"].origin)
 
     # Add Ethernet ---------------------------------------------------------------------------------
-    def add_ethernet(self, name="ethmac", phy=None, phy_cd="eth", dynamic_ip=False, software_debug=False):
+    def add_ethernet(self, name="ethmac", phy=None, phy_cd="eth", dynamic_ip=False, software_debug=False, nrxslots=2, ntxslots=2):
         # Imports
         from liteeth.mac import LiteEthMAC
 
@@ -1369,12 +1369,15 @@ class LiteXSoC(SoC):
             dw                = 32,
             interface         = "wishbone",
             endianness        = self.cpu.endianness,
-            with_preamble_crc = not software_debug)
+            with_preamble_crc = not software_debug,
+            nrxslots          = nrxslots,
+            ntxslots          = ntxslots)
         ethmac = ClockDomainsRenamer({
             "eth_tx": phy_cd + "_tx",
             "eth_rx": phy_cd + "_rx"})(ethmac)
         setattr(self.submodules, name, ethmac)
-        ethmac_region = SoCRegion(origin=self.mem_map.get(name, None), size=0x2000, cached=False)
+        ethmac_region_size = (ethmac.rx_slots.read()+ethmac.tx_slots.read())*ethmac.slot_size.read()
+        ethmac_region = SoCRegion(origin=self.mem_map.get(name, None), size=ethmac_region_size, cached=False)
         self.bus.add_slave(name=name, slave=ethmac.bus, region=ethmac_region)
         self.csr.add(name, use_loc_if_exists=True)
         if self.irq.enabled:
diff --git a/litex/tools/litex_json2dts.py b/litex/tools/litex_json2dts.py
index 4b944c757..046b47f84 100755
--- a/litex/tools/litex_json2dts.py
+++ b/litex/tools/litex_json2dts.py
@@ -200,7 +200,7 @@ def generate_dts(d, initrd_start=None, initrd_size=None, polling=False):
                 compatible = "litex,liteeth";
                 reg = <0x{ethmac_csr_base:x} 0x7c>,
                       <0x{ethphy_csr_base:x} 0x0a>,
-                      <0x{ethmac_mem_base:x} 0x2000>;
+                      <0x{ethmac_mem_base:x} 0x{ethmac_mem_size:x}>;
                 tx-fifo-depth = <{ethmac_tx_slots}>;
                 rx-fifo-depth = <{ethmac_rx_slots}>;
                 {ethmac_interrupt}
@@ -210,6 +210,7 @@ def generate_dts(d, initrd_start=None, initrd_size=None, polling=False):
     ethphy_csr_base  = d["csr_bases"]["ethphy"],
     ethmac_csr_base  = d["csr_bases"]["ethmac"],
     ethmac_mem_base  = d["memories"]["ethmac"]["base"],
+    ethmac_mem_size  = d["memories"]["ethmac"]["size"],
     ethmac_tx_slots  = d["constants"]["ethmac_tx_slots"],
     ethmac_rx_slots  = d["constants"]["ethmac_rx_slots"],
     ethmac_interrupt = "" if polling else "interrupts = <{}>;".format(d["constants"]["ethmac_interrupt"]))