diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py
index f9d152865..b9b2eab0b 100644
--- a/litex/soc/integration/soc.py
+++ b/litex/soc/integration/soc.py
@@ -1350,9 +1350,6 @@ class LiteXSoC(SoC):
 
         # USB ACM (with ValentyUSB core).
         elif uart_name in ["usb_acm"]:
-            # FIXME: do proper install of ValentyUSB.
-            os.system("git clone https://github.com/litex-hub/valentyusb -b hw_cdc_eptri")
-            sys.path.append("valentyusb")
             import valentyusb.usbcore.io as usbio
             import valentyusb.usbcore.cpu.cdc_eptri as cdc_eptri
             usb_pads  = self.platform.request("usb")
diff --git a/litex_setup.py b/litex_setup.py
index dce982ced..221c4eeda 100755
--- a/litex_setup.py
+++ b/litex_setup.py
@@ -76,6 +76,7 @@ git_repos = {
     # ------------------
     "pythondata-software-picolibc":    GitRepo(url="https://github.com/litex-hub/", clone="recursive"),
     "pythondata-software-compiler_rt": GitRepo(url="https://github.com/litex-hub/"),
+    "valentyusb":                      GitRepo(url="https://github.com/litex-hub/"), 
     "litex":                           GitRepo(url="https://github.com/enjoy-digital/", tag=True),
 
     # LiteX Cores Ecosystem.